This website requires JavaScript.
Explore
Help
Sign In
iHore
/
vLLM
Watch
8
Star
0
Fork
0
Code
Issues
Pull Requests
Actions
1
Packages
Projects
Releases
Wiki
Activity
Files
c0c25e25fa93ee7c3f279abbba5597c0fafa74ee
vLLM
/
vllm
/
platforms
T
History
Li, Jiang
and
Isotr0py
ff47aab056
[CPU] Upgrade CPU backend to torch-2.6 (
#13381
)
...
Signed-off-by: jiang1.li <
jiang1.li@intel.com
> Co-authored-by: Isotr0py <
2037008807@qq.com
>
2025-03-12 10:41:13 +00:00
..
__init__.py
[platforms] improve rocm debugging info (
#14257
)
2025-03-04 21:32:18 -08:00
cpu.py
[CPU] Upgrade CPU backend to torch-2.6 (
#13381
)
2025-03-12 10:41:13 +00:00
cuda.py
dynamic distpatch of fp8 kernels (
#14245
)
2025-03-11 10:54:56 -04:00
hpu.py
[platform] add base class for communicators (
#13208
)
2025-02-16 22:14:22 +08:00
interface.py
dynamic distpatch of fp8 kernels (
#14245
)
2025-03-11 10:54:56 -04:00
neuron.py
[Neuron] Add Neuron device communicator for vLLM v1 (
#14085
)
2025-03-10 18:37:04 -07:00
openvino.py
[Misc] set single whitespace between log sentences (
#13771
)
2025-02-25 10:26:12 +08:00
rocm.py
dynamic distpatch of fp8 kernels (
#14245
)
2025-03-11 10:54:56 -04:00
tpu.py
[Misc][Platform] Move use allgather to platform (
#14010
)
2025-03-03 15:40:04 +08:00
xpu.py
[Misc] set single whitespace between log sentences (
#13771
)
2025-02-25 10:26:12 +08:00