SeongJun Leeandlesj0610 a98247ab4d [Model] Drop the 4x M-RoPE cache headroom for Qwen3-VL, Qwen3.5 and Qwen3.8 (#59853) ...

Signed-off-by: lesj0610 <lesj0610@users.noreply.github.com>
Signed-off-by: lesj0610 <lesj0610@gmail.com>
Co-authored-by: lesj0610 <lesj0610@users.noreply.github.com>

2026-10-10 06:51:52 +00:00

..

ops

[ROCm][Perf] Fuse main QK-norm/RoPE/gate and KV-cache write into the AMD QSA prepare launch (#59732)

2026-10-09 21:14:49 +08:00

__init__.py

[Model] Support Qwen3.8-Flash-Next (#53896)

2026-08-31 05:57:56 +00:00

hyperconnection.py

[Model] Support Qwen3.8-Flash-Next (#53896)

2026-08-31 05:57:56 +00:00

indexer_qsa.py

[ROCm][Perf] Fuse main QK-norm/RoPE/gate and KV-cache write into the AMD QSA prepare launch (#59732)

2026-10-09 21:14:49 +08:00

low_latency_gemm.py

Add pydocstyle to the ruff rules (#52136)

2026-09-16 16:44:29 +00:00

model_state.py

[Model] Support Qwen3.8-Flash-Next (#53896)

2026-08-31 05:57:56 +00:00

model.py

[ROCm][Qwen4Exp] Use fused PLE Triton kernels on the AMD backend (#60021)

2026-10-08 15:47:56 +00:00

mtp.py

[ROCm][Qwen4Exp] Use fused PLE Triton kernels on the AMD backend (#60021)

2026-10-08 15:47:56 +00:00

ple_layer.py

[ROCm][Qwen4Exp] Use fused PLE Triton kernels on the AMD backend (#60021)

2026-10-08 15:47:56 +00:00

qsa.py

[Model] Drop the 4x M-RoPE cache headroom for Qwen3-VL, Qwen3.5 and Qwen3.8 (#59853)

2026-10-10 06:51:52 +00:00