Akshat TripathiandChengji Yao c20ef40fd0 [Hardware][TPU][V1] Multi-LoRA implementation for the V1 TPU backend (#14238) ...

Signed-off-by: Akshat Tripathi <akshat@krai.ai>
Signed-off-by: Chengji Yao <chengjiyao@google.com>
Co-authored-by: Chengji Yao <chengjiyao@google.com>

2025-05-07 16:28:47 -04:00

..

attention

[Kernel] Unified Triton kernel that doesn't distinguish between prefill + decode (#16828)

2025-05-06 18:21:48 -04:00

core

[v1] Introduce KVCacheBlocks as interface between Scheduler and KVCacheManager (#17479)

2025-05-06 08:50:34 -07:00

engine

Add full API docs and improve the UX of navigating them (#17485)

2025-05-03 19:42:43 -07:00

executor

[V1][PP] Support PP for MultiprocExecutor (#14219)

2025-05-06 07:58:05 -07:00

metrics

[V1][Bugfix]: vllm v1 verison metric num_gpu_blocks is None (#15755)

2025-04-30 18:20:39 +08:00

sample

[Bugfix] Fix triton import with local TritonPlaceholder (#17446)

2025-05-06 17:53:09 +08:00

spec_decode

[Misc] Split model loader (#17712)

2025-05-07 12:42:26 +08:00

stats

Update deprecated Python 3.8 typing (#13971)

2025-03-02 17:34:51 -08:00

structured_output

[V1][Feature] Enable Speculative Decoding with Structured Outputs (#14702)

2025-04-30 00:02:10 +00:00

worker

[Hardware][TPU][V1] Multi-LoRA implementation for the V1 TPU backend (#14238)

2025-05-07 16:28:47 -04:00

__init__.py

[V1] AsyncLLM Implementation (#9826)

2024-11-11 23:05:38 +00:00

kv_cache_interface.py

[V1] Implement sliding window attention in kv_cache_manager (#14097)

2025-04-01 00:33:17 -07:00

outputs.py

[V1] Aggregate chunked prompt logprobs in model runner (#14875)

2025-03-24 12:27:57 -04:00

request.py

[Core] Prevent side-channel attacks via cache salting (#17045)

2025-04-30 20:27:21 +08:00

serial_utils.py

[V1] Allow turning off pickle fallback in vllm.v1.serial_utils (#17427)

2025-04-30 16:10:54 +00:00

utils.py

[V1] Move usage stats to worker and start logging TPU hardware (#16211)

2025-04-25 14:06:01 -06:00