Chen Zhang c765f0b443 [FlashInfer] Avoid FlashInfer block_size 16 + head_size 256 on blackwell (#27994) ...

Signed-off-by: Chen Zhang <zhangch99@outlook.com>

2025-11-05 09:25:32 -08:00

..

layers

[XPU] Enable custom routing functions in IPEX for Llama4 (#28004)

2025-11-05 13:39:57 +00:00

model_loader

[V0 deprecation] Remove VLLM_USE_V1 usage in most modules (#27955)

2025-11-04 20:51:16 -08:00

models

[FlashInfer] Avoid FlashInfer block_size 16 + head_size 256 on blackwell (#27994)

2025-11-05 09:25:32 -08:00

warmup

[Kernels] Isolate modular kernel code from FusedMoEMethodBase subclasses. (#27123)

2025-11-04 21:59:45 +08:00

__init__.py

Convert formatting to use ruff instead of yapf + isort (#26247)

2025-10-05 07:06:22 -07:00

custom_op.py

[FrontEnd] UNREVERT CompilationConfig overhaul (#20283): deprecate use_inductor in favor of backend, simplify custom_ops (#26502)

2025-10-13 22:47:16 +00:00

parameter.py

[Docs] Replace rst style double-backtick with md single-backtick (#27091)

2025-10-17 02:47:34 -07:00

utils.py

[Chore] Clean up pytorch helper functions in vllm.utils (#26908)

2025-10-18 09:48:22 -07:00