Rehan KhanandLi, Jiang <jiang1.li@intel.com> 583637f126 [CPU][Perf] Add vectorized Sampler Kernel (#53913) ...

Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>

2026-09-30 15:16:28 +08:00

..

logits_processor

[Bugfix][LogitsProcessor] Validate ':' separator in custom logits processor FQCN (#56020)

2026-09-25 01:49:20 +00:00

ops

[CPU][Perf] Add vectorized Sampler Kernel (#53913)

2026-09-30 15:16:28 +08:00

__init__.py

[V1] Implement vLLM V1 [1/N] (#9289)

2024-10-22 01:24:07 -07:00

metadata.py

[Reasoning] Support for speculative decoding with thinking budget (#34668)

2026-04-29 06:14:52 +00:00

rejection_sampler.py

Add pydocstyle to the ruff rules (#52136)

2026-09-16 16:44:29 +00:00

sampler.py

[CPU][Perf] Add vectorized Sampler Kernel (#53913)

2026-09-30 15:16:28 +08:00

thinking_budget_state.py

[Bugfix][Sampling] Clear empty side on thinking-budget asymmetric SWAP (#49613)

2026-08-15 21:13:02 +00:00