Isotr0pyandCyrus Leung def232e122 [VLM] Clean up Phi-4-MM ViT implementation (#14812) ...

Signed-off-by: Isotr0py <2037008807@qq.com>
Co-authored-by: Cyrus Leung <tlleungac@connect.ust.hk>

2025-03-15 18:53:52 -07:00

..

build.txt

[Build/CI] Upgrade jinja2 to get 3 moderate CVE fixes (#14839)

2025-03-15 05:38:19 +00:00

common.txt

[VLM] Limit multimodal input cache by memory (#14805)

2025-03-15 02:52:05 -07:00

cpu.txt

[CPU] Upgrade CPU backend to torch-2.6 (#13381)

2025-03-12 10:41:13 +00:00

cuda.txt

Update to torch==2.6.0 (#12721)

2025-03-14 16:58:30 -04:00

dev.txt

Move requirements into their own directory (#12547)

2025-03-08 16:44:35 +00:00

docs.txt

[VLM] Limit multimodal input cache by memory (#14805)

2025-03-15 02:52:05 -07:00

hpu.txt

Move requirements into their own directory (#12547)

2025-03-08 16:44:35 +00:00

lint.txt

Move requirements into their own directory (#12547)

2025-03-08 16:44:35 +00:00

neuron.txt

Move requirements into their own directory (#12547)

2025-03-08 16:44:35 +00:00

openvino.txt

Move requirements into their own directory (#12547)

2025-03-08 16:44:35 +00:00

rocm-build.txt

[Build/CI] Upgrade jinja2 to get 3 moderate CVE fixes (#14839)

2025-03-15 05:38:19 +00:00

rocm-test.txt

Re-enable the AMD Entrypoints Test (#14711)

2025-03-14 12:18:13 -07:00

rocm.txt

Move requirements into their own directory (#12547)

2025-03-08 16:44:35 +00:00

test.in

[VLM] Clean up Phi-4-MM ViT implementation (#14812)

2025-03-15 18:53:52 -07:00

test.txt

[VLM] Clean up Phi-4-MM ViT implementation (#14812)

2025-03-15 18:53:52 -07:00

tpu.txt

[Build/CI] Upgrade jinja2 to get 3 moderate CVE fixes (#14839)

2025-03-15 05:38:19 +00:00

xpu.txt

[Build/CI] Upgrade jinja2 to get 3 moderate CVE fixes (#14839)

2025-03-15 05:38:19 +00:00