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vLLM/docs/features
8322d4e47f Enable Cross layers KV cache layout at NIXL Connector V2 (#33339)
Signed-off-by: Liran Schour <lirans@il.ibm.com>
Signed-off-by: liranschour <liranschour@users.noreply.github.com>
Co-authored-by: Or Ozeri <or@ozery.com>
Co-authored-by: Nicolò Lucchesi <nicolo.lucchesi@gmail.com>
Co-authored-by: Nicolò Lucchesi <nlucches@redhat.com>
2026-02-05 02:17:02 -08:00
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Features

Compatibility Matrix

The tables below show mutually exclusive features and the support on some hardware.

The symbols used have the following meanings:

  • ✅ = Full compatibility
  • 🟠 = Partial compatibility
  • ❌ = No compatibility
  • ❔ = Unknown or TBD

!!! note Check the ❌ or 🟠 with links to see tracking issue for unsupported feature/hardware combination.

Feature x Feature

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Feature CP APC LoRA SD CUDA graph pooling enc-dec logP prmpt logP async output multi-step mm best-of beam-search prompt-embeds
CP ✅
APC ✅ ✅
LoRA ✅ ✅ ✅
SD ✅ ✅ ❌ ✅
CUDA graph ✅ ✅ ✅ ✅ ✅
pooling 🟠* 🟠* ✅ ❌ ✅ ✅
enc-dec ❌ ❌ ❌ ❌ ✅ ✅ ✅
logP ✅ ✅ ✅ ✅ ✅ ❌ ✅ ✅
prmpt logP ✅ ✅ ✅ ✅ ✅ ❌ ✅ ✅ ✅
async output ✅ ✅ ✅ ❌ ✅ ❌ ❌ ✅ ✅ ✅
multi-step ❌ ✅ ❌ ❌ ✅ ❌ ❌ ✅ ✅ ✅ ✅
mm ✅ ✅ 🟠^ ❔ ✅ ✅ ✅ ✅ ✅ ✅ ❔ ✅
best-of ✅ ✅ ✅ ❌ ✅ ❌ ✅ ✅ ✅ ❔ ❌ ✅ ✅
beam-search ✅ ✅ ✅ ❌ ✅ ❌ ✅ ✅ ✅ ❔ ❌ ❔ ✅ ✅
prompt-embeds ✅ ✅ ✅ ❌ ✅ ❌ ❌ ✅ ❌ ❔ ❔ ❌ ❔ ❔ ✅

* Chunked prefill and prefix caching are only applicable to last-token or all pooling with causal attention.
^ LoRA is only applicable to the language backbone of multimodal models.

Feature x Hardware

Feature Volta Turing Ampere Ada Hopper CPU AMD Intel GPU
CP ❌ ✅ ✅ ✅ ✅ ✅ ✅ ✅
APC ❌ ✅ ✅ ✅ ✅ ✅ ✅ ✅
LoRA ✅ ✅ ✅ ✅ ✅ ✅ ✅ ✅
SD ✅ ✅ ✅ ✅ ✅ ❌ ✅ ✅
CUDA graph ✅ ✅ ✅ ✅ ✅ ❌ ✅ ❌
pooling ✅ ✅ ✅ ✅ ✅ ✅ ✅ ✅
enc-dec ✅ ✅ ✅ ✅ ✅ ✅ ❌ ✅
mm ✅ ✅ ✅ ✅ ✅ ✅ ✅ ✅
prompt-embeds ✅ ✅ ✅ ✅ ✅ ✅ ❔ ✅
logP ✅ ✅ ✅ ✅ ✅ ✅ ✅ ✅
prmpt logP ✅ ✅ ✅ ✅ ✅ ✅ ✅ ✅
async output ✅ ✅ ✅ ✅ ✅ ❌ ❌ ✅
multi-step ✅ ✅ ✅ ✅ ✅ ❌ ✅ ✅
best-of ✅ ✅ ✅ ✅ ✅ ✅ ✅ ✅
beam-search ✅ ✅ ✅ ✅ ✅ ✅ ✅ ✅

!!! note For information on feature support on Google TPU, please refer to the TPU-Inference Recommended Models and Features documentation.