Chaojun Zhang 2725c84aae [XPU] Enable sequence parallel support for XPU (#38608) ...

Signed-off-by: chaojun-zhang <chaojun.zhang@intel.com>
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Signed-off-by: Chaojun,Zhang <chaojun.zhang@intel.com>

2026-06-14 19:26:46 -07:00

..

__init__.py

[Platform] Fix RISC-V platform detection (lscpu parsing + non-NUMA meminfo) (#40427)

2026-04-24 04:33:05 +00:00

cpu.py

[Bugfix] Fix gemma4 crash on CPU: guard mem_get_info call (#44615)

2026-06-05 12:47:56 +00:00

cuda.py

[Feat] Add support for per GPU worker RDMA NIC selection (#42083)

2026-05-28 12:45:23 -07:00

interface.py

[10c/n] Migrate MoE kernels to torch stable ABI (#44565)

2026-06-10 23:02:26 -07:00

rocm.py

[Migration] Migrate GGUF quantization support to plugin (#39612)

2026-06-12 12:02:21 -07:00

tpu.py

[Refactor][TPU] Remove torch_xla path and use tpu-inference (#30808)

2026-01-07 16:07:16 +08:00

xpu.py

[XPU] Enable sequence parallel support for XPU (#38608)

2026-06-14 19:26:46 -07:00

zen_cpu.py

[ZenCPU] AMD Zen CPU Backend with supported dtypes via zentorch weekly (#39967)

2026-04-18 06:22:37 +00:00