Chendi.Xue 460d02a417 [NIXL] Fix after virtual block_size for host_buffer with heter kv_layout (#29122) ...

Signed-off-by: Chendi Xue <chendi.xue@intel.com>

2025-11-21 08:55:27 -08:00

..

__init__.py

[TPU] Rename path to tpu platform (#28452)

2025-11-11 19:16:47 +00:00

cpu.py

[Misc] Make SchedulerConfig.max_model_len init-only (#28733)

2025-11-15 01:59:31 -08:00

cuda.py

[Attention] FlashAttention ViT support, make default backend (#28763)

2025-11-18 20:06:21 -08:00

interface.py

[CI Failure] Fix backend selection for encoder-only models (#28534)

2025-11-13 10:11:27 -05:00

rocm.py

[Attention] Add ROCM_AITER_MLA_SPARSE to attention backend registry (#29103)

2025-11-20 20:24:43 -08:00

tpu.py

[Misc] Make SchedulerConfig.max_model_len init-only (#28733)

2025-11-15 01:59:31 -08:00

xpu.py

[NIXL] Fix after virtual block_size for host_buffer with heter kv_layout (#29122)

2025-11-21 08:55:27 -08:00