Jialin Ouyang 30b9c67743 Revert "[Redo] #26368 (#28771)" (#29121) ...

Signed-off-by: Jialin Ouyang <Jialin.Ouyang@gmail.com>

2025-11-20 21:27:45 -08:00

..

logits_processor

[Core] Async Scheduling X Spec Decoding Compatibility (#24799)

2025-11-17 12:16:20 -08:00

ops

[AITER] [ROCm] Fix crash when loading llama4 model with old aiter version installed, fallback to forward_native implementation (#29124)

2025-11-20 17:54:35 -08:00

tpu

[V1][Spec Decode] Fix greedy temperature detection after sampler refactor (#27077)

2025-10-17 13:27:47 -07:00

__init__.py

[V1] Implement vLLM V1 [1/N] (#9289)

2024-10-22 01:24:07 -07:00

metadata.py

Update Optional[x] -> x | None and Union[x, y] to x | y (#26633)

2025-10-12 09:51:31 -07:00

rejection_sampler.py

Revert "[Redo] #26368 (#28771)" (#29121)

2025-11-20 21:27:45 -08:00

sampler.py

[Chore] Separate out vllm.utils.platform_utils.py (#27374)

2025-10-23 19:08:06 +00:00