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vLLM/vllm/platforms
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Ryan RockandMicah Williamson f43d7e1a0f [CI][AMD] Gate Aiter MHA FA on dtype (#60679)
Signed-off-by: Ryan Rock <ryan.rock@amd.com>
Co-authored-by: Micah Williamson <micah.williamson@amd.com>
2026-10-13 18:55:19 -05:00
..
__init__.py
Add pydocstyle to the ruff rules (#52136)
2026-09-16 16:44:29 +00:00
cpu.py
[Attention] Remove cascade attention (#61126)
2026-10-12 10:41:07 -07:00
cuda.py
[Attention] Enable FA4 sparse MQA decode on Blackwell (#55866)
2026-10-13 09:31:37 -04:00
interface.py
[KV Cache] GLM-5.3-Flash: use the generic packed KV layout; CircularBufferSpec tail with speculative ring slots (#57169)
2026-10-09 15:48:37 -04:00
rocm.py
[CI][AMD] Gate Aiter MHA FA on dtype (#60679)
2026-10-13 18:55:19 -05:00
tpu.py
[Refactor][TPU] Remove torch_xla path and use tpu-inference (#30808)
2026-01-07 16:07:16 +08:00
xpu.py
[XPU] fix online fp8_per_channel quantization (#56027)
2026-10-09 18:38:01 +08:00
zen_cpu.py
[ZenCPU] AMD Zen CPU Backend with supported dtypes via zentorch weekly (#39967)
2026-04-18 06:22:37 +00:00
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