Logo
Explore Help
Sign In
iHore/vLLM
Watch 8
Star 0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity
Files
de92d916fe8a897b00a8adb0aab9ed9ec99f2b6c
vLLM/tests/compile/piecewise
T
History
Boyuan FengandHarry Mellor f57438338d [BugFix] Patch inductor memory plan logic (#26878)
Signed-off-by: Boyuan Feng <boyuan@meta.com>
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
Co-authored-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
2025-10-15 12:51:45 +00:00
..
__init__.py
[torch.compile] rework compile control with piecewise cudagraph (#9715)
2024-10-29 23:03:49 -07:00
test_full_cudagraph.py
[torch.compile] Fix tests for torch==2.9 inductor partition (#26116)
2025-10-14 19:55:02 -04:00
test_multiple_graphs.py
[BugFix] Patch inductor memory plan logic (#26878)
2025-10-15 12:51:45 +00:00
test_simple.py
[Frontend][torch.compile] CompilationConfig Overhaul (#20283): name change compilation level to compilation mode, deprecation compilation level (#26355)
2025-10-15 02:51:16 +00:00
test_toy_llama.py
[Frontend][torch.compile] CompilationConfig Overhaul (#20283): name change compilation level to compilation mode, deprecation compilation level (#26355)
2025-10-15 02:51:16 +00:00
Powered by Gitea Version: 1.27.2 Page: 248ms Template: 5ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API