Michael FeilandRoger Wang c2b4a1bce9 [Doc] Add typing hints / mypy types cleanup (#3816) ...

Co-authored-by: Roger Wang <136131678+ywang96@users.noreply.github.com>

2024-04-11 17:17:21 -07:00

..

fused_moe

[Kernel] Fused MoE Config for Mixtral 8x22 (#4002)

2024-04-11 07:50:00 -07:00

ops

[CI] Try introducing isort. (#3495)

2024-03-25 07:59:47 -07:00

quantization

[Core] Set linear_weights directly on the layer (#3977)

2024-04-11 16:35:51 -04:00

__init__.py

Change the name to vLLM (#150)

2023-06-17 03:07:40 -07:00

activation.py

[Misc] Add indirection layer for custom ops (#3913)

2024-04-10 20:26:07 -07:00

layernorm.py

[Misc] Add indirection layer for custom ops (#3913)

2024-04-10 20:26:07 -07:00

linear.py

[Core] Set linear_weights directly on the layer (#3977)

2024-04-11 16:35:51 -04:00

logits_processor.py

[Core][Refactor] move parallel_utils into vllm/distributed (#3950)

2024-04-10 15:33:30 -07:00

rejection_sampler.py

[CI] Try introducing isort. (#3495)

2024-03-25 07:59:47 -07:00

rotary_embedding.py

[Doc] Add typing hints / mypy types cleanup (#3816)

2024-04-11 17:17:21 -07:00

sampler.py

[Bugfix] handle prompt_logprobs in _apply_min_tokens_penalty (#3876)

2024-04-10 01:39:56 -07:00

vocab_parallel_embedding.py

[Core][Refactor] move parallel_utils into vllm/distributed (#3950)

2024-04-10 15:33:30 -07:00