Logo
Explore Help
Sign In
iHore/vLLM
Watch 8
Star 0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity
Files
e45c8a9f4bad29472991ef01b2fa754a2f565723
vLLM/vllm/platforms
T
History
Tianmu LiClaude Sonnet 4.6Li, Jiang <jiang1.li@intel.com>
1aad125815 [CPU] Enable chunked prefill and prefix caching for qwen3.5 (#46202)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: Claude Sonnet 4.6 (1M context) <noreply@anthropic.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
2026-06-25 03:49:21 +00:00
..
__init__.py
[Core] Ensure memory is pinned prior to async h2d copy (#45424)
2026-06-20 20:02:24 -07:00
cpu.py
[CPU] Enable chunked prefill and prefix caching for qwen3.5 (#46202)
2026-06-25 03:49:21 +00:00
cuda.py
[Log] Update to log once (#46511)
2026-06-24 14:45:16 +00:00
interface.py
[Log] Update to log once (#46511)
2026-06-24 14:45:16 +00:00
rocm.py
[ROCm] Remove erroneous inclusion of gptq_marlin as supported quant scheme on ROCm (#46655)
2026-06-24 21:27:19 -05:00
tpu.py
[Refactor][TPU] Remove torch_xla path and use tpu-inference (#30808)
2026-01-07 16:07:16 +08:00
xpu.py
[Log] Update to log once (#46511)
2026-06-24 14:45:16 +00:00
zen_cpu.py
[ZenCPU] AMD Zen CPU Backend with supported dtypes via zentorch weekly (#39967)
2026-04-18 06:22:37 +00:00
Powered by Gitea Version: 1.27.2 Page: 218ms Template: 6ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API