typer-JandLi, Jiang <jiang1.li@intel.com> 4184653775 feat: add RISC-V support for CPU backend (v2) (#36578) ...

Signed-off-by: typer-J <2236066784@qq.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>

2026-03-10 21:51:39 -07:00

..

external_projects

[BugFix] Fix cmake based incremental install (wrong vllm install dir) (#35773)

2026-03-02 21:58:16 -08:00

cpu_extension.cmake

feat: add RISC-V support for CPU backend (v2) (#36578)

2026-03-10 21:51:39 -07:00

hipify.py

Convert formatting to use ruff instead of yapf + isort (#26247)

2025-10-05 07:06:22 -07:00

utils.cmake

[CPU][FIX] Fix build failures on Arm CPUs with torch nightly (#30481)

2025-12-12 02:09:25 +00:00