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iHore/vLLM
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vLLM/vllm/v1/core
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yue.yuandBenjamin Chislett e7c9df9449 [Bugfix][Structured Output][Spec Decode] Constrain bitmask and trim grammar advance at the reasoning boundary (#44297)
Signed-off-by: Allen.Yu <yuyue0225sc@163.com>
Signed-off-by: yue.yu <yuyue0225sc@163.com>
Co-authored-by: Benjamin Chislett <chislett.ben@gmail.com>
2026-07-04 09:08:45 +00:00
..
sched
[Bugfix][Structured Output][Spec Decode] Constrain bitmask and trim grammar advance at the reasoning boundary (#44297)
2026-07-04 09:08:45 +00:00
__init__.py
[V1] Implement vLLM V1 [1/N] (#9289)
2024-10-22 01:24:07 -07:00
block_pool.py
[1/N][Core] add partial prefix cache primitives (#45939)
2026-06-21 23:43:10 -07:00
encoder_cache_manager.py
[Perf] Improve multimodal item handling from O(n) to O(log n) per step (#44212)
2026-06-03 11:00:26 +00:00
kv_cache_coordinator.py
[Model] Support Unlimited OCR (#46564)
2026-06-27 23:09:18 -07:00
kv_cache_manager.py
[Model] Support Unlimited OCR (#46564)
2026-06-27 23:09:18 -07:00
kv_cache_metrics.py
[Core][Observability] Add KV cache residency metrics (#27793)
2025-12-01 18:27:53 +00:00
kv_cache_utils.py
[KV Offload] Gate packed HMA KV cache on cross-layer config (#46252)
2026-06-24 11:55:30 -04:00
single_type_kv_cache_manager.py
[Model] Support Unlimited OCR (#46564)
2026-06-27 23:09:18 -07:00
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