Gabriel WuandClaude Opus 5.5 dcd07967ca [CPU] Keep the hybrid block size across the engine core's config rerun (#61805) ...

Signed-off-by: Zihua Wu <13583761+lucifer1004@users.noreply.github.com>
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>

2026-10-17 12:06:03 +08:00

..

__init__.py

Add pydocstyle to the ruff rules (#52136)

2026-09-16 16:44:29 +00:00

cpu.py

[CPU] Keep the hybrid block size across the engine core's config rerun (#61805)

2026-10-17 12:06:03 +08:00

cuda.py

[Bugfix][Platform] Fall back to torch when device-level NVML memory is unsupported (GB10) (#57378)

2026-10-14 12:45:29 +00:00

interface.py

[Core][Feat] Pluggable KVCacheConfigBuilder for platform/model-specific KV cache planning (#53558)

2026-10-16 23:16:47 +00:00

rocm.py

[ROCm][BugFix] Don't use AITER rms_norm as an IR OP on gfx90a when AITER always on. (#59290)

2026-10-14 12:48:37 -07:00

tpu.py

[Refactor][TPU] Remove torch_xla path and use tpu-inference (#30808)

2026-01-07 16:07:16 +08:00

xpu.py

[XPU][MLA] Integrate XPU MLA support into the existing FLASH_ATTN_MLA backend (#58297)

2026-10-15 12:47:37 +08:00

zen_cpu.py

[CPU][Zen] Update zentorch to 2.14.0.1 & enable float16 on Venice and later (#61411)

2026-10-15 00:23:50 -07:00