sychen52 7c5dc571cb [Attention][DSA] Enable W4A16 DSA (#51724) ...

Signed-off-by: Shiyang Chen <shiychen@nvidia.com>

2026-09-01 12:37:47 +08:00

..

determinism

[Perf] Autotune batch invariance triton kernel in blackwell, 33.6% E2E latency reduction (#53649)

2026-08-25 15:06:01 -04:00

hw_agnostic

Hardware-agnostic model definition via HF transformer backend (1/N) (#49458)

2026-08-13 11:21:50 +01:00

kernels

[Kernel] add Flashinfer cutedsl w4a16 linear (#53014)

2026-09-01 02:49:14 +00:00

layers

[Attention][DSA] Enable W4A16 DSA (#51724)

2026-09-01 12:37:47 +08:00

model_loader

[Model] Support Qwen3.8-Flash-Next (#53896)

2026-08-31 05:57:56 +00:00

models

[Bugfix][Spec Decode] Take the DFlash draft's RoPE layout from its own config (#54373)

2026-08-31 18:13:20 -04:00

offloader

[Offloader] Offload submodules that make_layers never reaches (#53120)

2026-08-26 18:37:00 +08:00

warmup

[Distributed] Add opt-in FlashInfer PCIe IPC all-reduce backend (#53576)

2026-09-01 03:34:56 +00:00

__init__.py

[Platform] Deprecate seed_everything (#31659)

2026-01-04 18:34:04 -08:00

custom_op.py

[Bugfix] Reject contradictory custom-op directives (#49134)

2026-07-26 08:42:14 -04:00

parameter.py

Speed up docs build (#44635)

2026-06-05 14:51:44 +00:00

utils.py

[Weight processing] Copy over new_data attributes in replace_parameter (#49601)

2026-08-06 13:03:37 -04:00