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f1899b2ffdf87598350c416a074c8c291c845902
vLLM
/
vllm
/
v1
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worker
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cpu
T
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Li, Jiang
90245f4190
[Bugfix] Fix multi-modal support on CPU MRV2 (
#50073
)
...
Signed-off-by: jiang1.li <
jiang1.li@intel.com
>
2026-07-28 06:09:48 +00:00
..
__init__.py
[CPU] Experimentally enable Triton and MRV2 (
#43225
)
2026-05-22 01:48:17 -07:00
buffer_utils.py
[CPU] Experimentally enable Triton and MRV2 (
#43225
)
2026-05-22 01:48:17 -07:00
model_runner.py
[CPU] Experimentally enable Triton and MRV2 (
#43225
)
2026-05-22 01:48:17 -07:00
shm.py
[Bugfix] Fix multi-modal support on CPU MRV2 (
#50073
)
2026-07-28 06:09:48 +00:00
