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iHore/vLLM
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f2145efcb6dc7b5ff0ec0a321508ec7f313c6f83
vLLM/vllm/engine
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Vibhav AgarwalXinyu ChenMichael Goin
f4b42df048 [Attention Backend] TurboQuant: 2-bit KV cache compression with 4x capacity (#38479)
Signed-off-by: vibhavagarwal5 <vibhavagarwal5@gmail.com>
Signed-off-by: Michael Goin <mgoin64@gmail.com>
Co-authored-by: Xinyu Chen <xinyu1.chen@intel.com>
Co-authored-by: Michael Goin <mgoin64@gmail.com>
2026-04-14 19:57:13 -07:00
..
__init__.py
Change the name to vLLM (#150)
2023-06-17 03:07:40 -07:00
arg_utils.py
[Attention Backend] TurboQuant: 2-bit KV cache compression with 4x capacity (#38479)
2026-04-14 19:57:13 -07:00
async_llm_engine.py
[Docs] Reduce time spent generating API docs (#34255)
2026-02-11 02:56:02 -08:00
llm_engine.py
[Docs] Reduce time spent generating API docs (#34255)
2026-02-11 02:56:02 -08:00
protocol.py
[Frontend][4/n] Improve pooling entrypoints | pooling. (#39153)
2026-04-09 10:09:45 +00:00
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