3 people f97be32d1d [VLM][Model] TP support for ViTs (#7186) ...

Co-authored-by: Roger Wang <136131678+ywang96@users.noreply.github.com>
Co-authored-by: Roger Wang <ywang@roblox.com>

2024-08-30 08:19:27 -07:00

..

guided_decoding

[misc][core] lazy import outlines (#7831)

2024-08-24 00:51:38 -07:00

layers

[Core] Logprobs support in Multi-step (#7652)

2024-08-29 19:19:08 -07:00

model_loader

[Core] Logprobs support in Multi-step (#7652)

2024-08-29 19:19:08 -07:00

models

[VLM][Model] TP support for ViTs (#7186)

2024-08-30 08:19:27 -07:00

__init__.py

[Performance] Optimize e2e overheads: Reduce python allocations (#7162)

2024-08-08 21:34:28 -07:00

custom_op.py

[XPU] fallback to native implementation for xpu custom op (#7670)

2024-08-20 00:26:09 -07:00

parameter.py

[Misc] update fp8 to use vLLMParameter (#7437)

2024-08-22 08:36:18 -04:00

pooling_metadata.py

[Model][Misc] Add e5-mistral-7b-instruct and Embedding API (#3734)

2024-05-11 11:30:37 -07:00

sampling_metadata.py

[Core] Optimize SPMD architecture with delta + serialization optimization (#7109)

2024-08-18 17:57:20 -07:00

utils.py

[Hardware][Neuron] Refactor neuron support (#3471)

2024-03-22 01:22:17 +00:00