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fb5ec0dc9edfdba54882575e33e2a4215bd295b9
vLLM
/
vllm
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platforms
T
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Michael Goin
and
Claude Fable 5
ecf4aa5ce2
[Bugfix] Fix FlashInfer non-causal draft attention (DFlash/DSpark) on Blackwell (
#48167
)
...
Signed-off-by: mgoin <
mgoin64@gmail.com
> Co-authored-by: Claude Fable 5 <
noreply@anthropic.com
>
2026-07-15 12:44:01 -07:00
..
__init__.py
[Core] Ensure memory is pinned prior to async h2d copy (
#45424
)
2026-06-20 20:02:24 -07:00
cpu.py
[CPU] Create Proper Numa topology for s390x (
#40714
)
2026-07-13 12:58:43 +08:00
cuda.py
[Bugfix] Fix FlashInfer non-causal draft attention (DFlash/DSpark) on Blackwell (
#48167
)
2026-07-15 12:44:01 -07:00
interface.py
Fix NVML capability lookup for visible devices (
#47892
)
2026-07-08 09:07:44 -04:00
rocm.py
[2/N][KV-Cache Layout Refactor] Pack K/V into the content dim across attention backends (
#44455
)
2026-07-11 11:11:16 -04:00
tpu.py
[Refactor][TPU] Remove torch_xla path and use tpu-inference (
#30808
)
2026-01-07 16:07:16 +08:00
xpu.py
[XPU] [Fusion passes] Disable fuse_rope_kvcache_cat_mla & qk_norm_rope_ fusion on XPU (
#47962
)
2026-07-08 09:23:06 +00:00
zen_cpu.py
[ZenCPU] AMD Zen CPU Backend with supported dtypes via zentorch weekly (
#39967
)
2026-04-18 06:22:37 +00:00