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fcaa84efa7a980cee3681976ecfe36133c48251a
vLLM/vllm/model_executor
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Nick Hillandziminghuang fcaa84efa7 [BugFix] Gate MRV2 mixed sparse-MLA warmup on max_num_seqs > 1 (#47050)
Signed-off-by: Nick Hill <nickhill123@gmail.com>
Co-authored-by: ziminghuang <ziminghuang@inferact.ai>
2026-06-30 16:31:27 +01:00
..
kernels
[CPU][RISC-V] Add RVV path for W4A8 INT4 GEMM (#45269)
2026-06-25 08:18:10 +00:00
layers
[Bugfix][Quant] Raise actionable error instead of bare assert for group-size/TP mismatch (#46230) (#46236)
2026-06-30 14:57:14 +00:00
model_loader
Remove more unnecessary load_weights methods (#47058)
2026-06-30 15:22:16 +01:00
models
[Spec Decode] Fix hidden-state extraction block size for hybrid verifiers (#46301)
2026-06-30 08:19:51 -07:00
offloader
[Refactor] Clean up log once scope="local" (#40540)
2026-04-22 16:42:43 -04:00
warmup
[BugFix] Gate MRV2 mixed sparse-MLA warmup on max_num_seqs > 1 (#47050)
2026-06-30 16:31:27 +01:00
__init__.py
[Platform] Deprecate seed_everything (#31659)
2026-01-04 18:34:04 -08:00
custom_op.py
Add ability to replace oot ops when using lora (#37181)
2026-03-16 18:04:15 -07:00
parameter.py
Speed up docs build (#44635)
2026-06-05 14:51:44 +00:00
utils.py
Remove more unnecessary load_weights methods (#47058)
2026-06-30 15:22:16 +01:00
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