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fe4c5dcd4cc71c2c1dc05375be497e413425aad7
vLLM/vllm/model_executor/kernels
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zofia fe4c5dcd4c [XPU] [Bugfix] process ragged weights in xpu linear backend (#52118)
Signed-off-by: Zhu, Zufang <zufang.zhu@intel.com>
2026-08-14 09:11:43 +08:00
..
attention
[Attention][DSA] support dcp for FLASHINFER_MLA_SPARSE (#46076)
2026-07-01 00:32:20 -04:00
linear
[XPU] [Bugfix] process ragged weights in xpu linear backend (#52118)
2026-08-14 09:11:43 +08:00
mhc
[ROCm] Defer tilelang import through its import from vllm.tilelang_utils import tilelang and relaxed has_tilelang (#51159)
2026-08-13 13:12:40 -05:00
__init__.py
[Refactor] [1/N] Reorganize kernel abstraction directory (#34055)
2026-02-24 06:47:22 +00:00
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