[Bugfix][NVFP4 MoE] Pad gated intermediate to 64 for FlashInfer TRT-LLM shuffle (M%128) (#46880)
Signed-off-by: Mike G <180722391+mikekg@users.noreply.github.com>
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@@ -353,7 +353,13 @@ def prepare_nvfp4_moe_layer_for_fi_or_cutlass(
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layer.moe_config.hidden_dim = padded_hidden
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# Align weights for FI NVFP4 MoE kernels.
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min_alignment = 16 if is_gated else 128
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# FlashInfer's TRT-LLM block-scale shuffle asserts the gate/up row dim
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# (= up_mult * padded_intermediate, up_mult=2 when gated) is a multiple of
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# 128. So gated needs padded_intermediate % 64 (2*64=128); the old value 16
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# left 2*intermediate a multiple of only 32, so an NVFP4 MoE whose rank-local
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# intermediate is not 128-aligned at TP>1 (e.g. Gemma-4-26B-A4B at tp4) hit
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# `assert M % 128 == 0`. Padded rows are zero -> outputs unchanged.
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min_alignment = 64 if is_gated else 128
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w13, w13_scale, w2, w2_scale, padded_intermediate = (
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align_fp4_moe_weights_for_fi(
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w13, w13_scale, w2, w2_scale, is_act_and_mul, min_alignment
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