[CI][NIXL] Isolate concurrent engine internal ports (#49129)
Signed-off-by: Andreas Karatzas <Andreas.Karatzas@amd.com> Co-authored-by: OpenAI Codex <noreply@openai.com>
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OpenAI Codex
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@@ -83,6 +83,11 @@ DECODE_BLOCK_SIZE=${DECODE_BLOCK_SIZE:-128}
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ENFORCE_EAGER=${ENFORCE_EAGER:-1}
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# Comma-separated extra args for vllm serve (e.g. --max-model-len,2048)
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VLLM_SERVE_EXTRA_ARGS=${VLLM_SERVE_EXTRA_ARGS:-}
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# Pin concurrent prefiller and non-DP decoder engines to separate internal
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# port windows. DP decoder ranks retain their existing internal port selection.
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PREFILLER_INTERNAL_PORT_BASE=${PREFILLER_INTERNAL_PORT_BASE:-20000}
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DECODER_INTERNAL_PORT_BASE=${DECODER_INTERNAL_PORT_BASE:-30000}
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INTERNAL_PORT_STRIDE=${INTERNAL_PORT_STRIDE:-100}
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# Resolve the repository root from the script location instead of `.git`.
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# The ROCm CI image copies `/vllm-workspace` without the Git metadata, so
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@@ -154,12 +159,14 @@ run_tests_for_model() {
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PORT=$((8100 + i))
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# Calculate side channel port. Avoid clash with with TP workers.
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SIDE_CHANNEL_PORT=$((5559 + i))
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INTERNAL_PORT=$((PREFILLER_INTERNAL_PORT_BASE + i * INTERNAL_PORT_STRIDE))
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echo "Starting prefill instance $i on GPU $GPU_ID, port $PORT"
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# Build the command with or without model-specific args
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BASE_CMD="CUDA_VISIBLE_DEVICES=$GPU_ID \
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VLLM_KV_CACHE_LAYOUT='HND' \
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VLLM_PORT=$INTERNAL_PORT \
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UCX_NET_DEVICES=all \
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VLLM_NIXL_SIDE_CHANNEL_PORT=$SIDE_CHANNEL_PORT \
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vllm serve $model_name \
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@@ -208,12 +215,18 @@ run_tests_for_model() {
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PORT=$((8200 + i))
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# Calculate side channel port
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SIDE_CHANNEL_PORT=$((5659 + i * $DECODER_TP_SIZE))
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INTERNAL_PORT=$((DECODER_INTERNAL_PORT_BASE + i * INTERNAL_PORT_STRIDE))
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DECODER_INTERNAL_PORT_ENV=
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if [[ -z "${DP_EP:-}" ]]; then
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DECODER_INTERNAL_PORT_ENV="VLLM_PORT=$INTERNAL_PORT"
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fi
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echo "Starting decode instance $i on GPU $GPU_ID, port $PORT"
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# Build the command with or without model-specific args
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BASE_CMD="CUDA_VISIBLE_DEVICES=$GPU_ID \
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VLLM_KV_CACHE_LAYOUT=$DECODER_KV_LAYOUT \
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$DECODER_INTERNAL_PORT_ENV \
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UCX_NET_DEVICES=all \
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VLLM_NIXL_SIDE_CHANNEL_PORT=$SIDE_CHANNEL_PORT \
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vllm serve $model_name \
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