 Thien Tran
|
82b9ccaa79
|
[Perf][MoE] Skip the TRTLLM fp8-block activation-scale transpose copy (#61773)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-10-15 12:09:07 -07:00 |
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Thien TranandKimi Code
|
937d6c19df
|
[Perf][GDN] Skip FLA chunk metadata when FlashInfer GDN prefill is active (#61569)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Kimi Code <noreply@moonshot.cn>
|
2026-10-14 01:46:54 -07:00 |
|
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Thien Tran
|
0fae39a014
|
[Perf] per_token_group_quant_8bit: multiply by reciprocal instead of dividing per element (#61343)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-10-13 21:37:10 +08:00 |
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Thien TranandOpenAI Codex
|
656d0d4506
|
[Perf] Tune Triton GDN decode tiles on SM100-family GPUs (#61355)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: OpenAI Codex <noreply@openai.com>
|
2026-10-13 17:01:12 +08:00 |
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|
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042ab0305c
|
[Perf][Qwen4Exp] Merge QSA QKVG and indexer QK projections (#59533)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Codex <noreply@openai.com>
Co-authored-by: namgyu-youn <namgyu.dev@gmail.com>
|
2026-10-05 07:03:29 +00:00 |
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|
Thien Tranandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
8873ac83bb
|
[Docs] Add @gau-nernst to CODEOWNERS and committers (#59369)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
2026-09-30 16:23:40 +00:00 |
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Thien Tran
|
d6cce94fd4
|
[Perf][Qwen4Exp] Fuse HC down projection and SiLU on NVIDIA (#58957)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-09-28 18:51:38 +08:00 |
|
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Thien TranandKimi
|
4694145045
|
[Skills] Update kernel-microbenchmark to include ROCm (#58646)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Kimi <noreply@moonshot.cn>
|
2026-09-28 14:18:38 +08:00 |
|
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Thien TranandCodex
|
55de40a2fc
|
[Minimax-M3] Add Encoder CUDA graph support (#58673)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Codex <codex@openai.com>
|
2026-09-28 04:17:36 +00:00 |
|
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Thien Tran
|
39d49539de
|
[KimiViT][Perf] Fuse per-layer QK RoPE into one in-place kernel (#58651)
|
2026-09-27 18:18:06 -07:00 |
|
|
Thien Tran
|
7a877ae34d
|
[Qwen3.8-Flash-Next] Avoid memory fragmentation in QSA indexer logits workspace (#57105)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-09-27 10:11:52 +08:00 |
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|
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16070ed7e9
|
[Minimax-M3][Perf] Use triton_mrope for vision tower + int64 offset fix for triton_mrope (#58526)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Kimi <noreply@moonshot.cn>
Co-authored-by: Isotr0py <Isotr0py@outlook.com>
|
2026-09-24 18:30:32 -07:00 |
|
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Thien Tran
|
ade1056ee5
|
[Kimi-K3][Perf] Dispatch GEMM for vision patch embedder (#58527)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-09-24 18:30:11 -07:00 |
|
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Thien TranandOpenAI Codex
|
00b7847c80
|
[Perf] Use Conv3dLayer for MiniMax M3 patch embedding (#58512)
Signed-off-by: OpenAI Codex <codex@openai.com>
Co-authored-by: OpenAI Codex <codex@openai.com>
|
2026-09-24 00:41:36 -07:00 |
|
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Thien TranandCodex
|
8da75d6190
|
C3x SM100 FP8 blockwise - Pad activation scales to multiple of 4 (#57377)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Codex <noreply@openai.com>
|
2026-09-18 08:39:27 +00:00 |
|
|
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41f9104fa6
|
[DSv4.1] Integrate Mega-Gate from DeepGEMM (#56266)
Signed-off-by: zjy0516 <riverclouds.zhu@qq.com>
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: OpenAI Codex <codex@openai.com>
Co-authored-by: zjy0516 <riverclouds.zhu@qq.com>
|
2026-09-17 12:06:36 -07:00 |
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|
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cc4210f671
|
[Perf] Improve BF16x3 router GEMM accuracy and make it default on sm100 (#55899)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: OpenAI Codex <noreply@openai.com>
Co-authored-by: Jee Jee Li <pandaleefree@gmail.com>
|
2026-09-09 07:33:12 -07:00 |
|
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Thien Tran
|
94e26dd3dd
|
[Qwen3.8-Flash-Next] Support FP8 indexer cache for QSA (#54890)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-09-07 12:15:45 +00:00 |
|
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Thien Tran
|
d9105ea800
|
[Qwen3.8-Flash-Next] Remove torch.compile for NVIDIA implementation (#55272)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-09-06 21:57:56 -07:00 |
|
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Thien TranandKimi
|
31a8a26662
|
[Qwen3.8-Flash-Next] Improve QSA sparse GQA for prefill and short-ctx decode (#54873)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Kimi <noreply@moonshot.cn>
|
2026-09-04 06:08:02 -07:00 |
|
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Thien Tran
|
a5c9179e73
|
[Qwen3.8-Flash-Next] Compact indexer logits workspace to improve prefill efficiency (#54915)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-09-04 00:43:20 -07:00 |
|
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Thien Tran
|
f4e6136146
|
[Kimi-K3] Bump FlashKDA to fix unstable inverse (#54859)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-09-02 00:16:29 -07:00 |
|
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Thien TranandCodex
|
f870b92976
|
[Qwen3.8-Flash-Next] Fuse Qwen4Exp PLE kernels (#54517)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Codex <codex@openai.com>
|
2026-09-02 12:32:16 +08:00 |
|
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Thien Tran
|
003e34341a
|
[Qwen3.8-Flash-Next] Separate prefill and decode paths for QSA indexer (#54513)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-09-02 09:08:10 +08:00 |
|
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Thien Tran
|
f956e1c343
|
[Kimi-K3][Bugfix] Fix low-latency GEMM fallback initialization (#54167)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-08-28 08:32:20 +00:00 |
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Thien Tran
|
6ec92bcbc8
|
[Kimi-K3] Merge MLA gate into QKV-A projection (#54015)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-08-27 17:47:18 -07:00 |
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Thien TranandCodex
|
d125b540b7
|
[Agents] Add CUDA IMA debugging skill (#53702)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Codex <codex@openai.com>
|
2026-08-25 18:09:24 -07:00 |
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Thien TranandCodex
|
5e379a361e
|
[Agents] Add kernel microbenchmark skill (#53688)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Codex <codex@openai.com>
|
2026-08-25 07:25:27 +00:00 |
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|
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2785c72a14
|
[Kimi-K3] Extend GEMM-RS to GEMM-AR (#53053)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: OpenAI Codex <codex@openai.com>
Co-authored-by: wzhao18 <wzhao18.sz@gmail.com>
|
2026-08-21 03:44:15 +00:00 |
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Thien TranandOpenAI Codex
|
6259572b28
|
[Docs] Use incremental builds for C++ changes in AGENTS.md (#53098)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: OpenAI Codex <codex@openai.com>
|
2026-08-20 04:08:50 -07:00 |
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Thien Tran
|
6014f9e672
|
[Kimi-K3] Add GEMM-RS for sequence parallelism (#52079)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-08-13 09:02:28 -07:00 |
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Thien TranandOpenAI Codex
|
9f3169960a
|
[MoE] Align TRTLLM MXFP4 autotune buckets (#50942)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: OpenAI Codex <noreply@openai.com>
|
2026-08-05 18:17:53 -07:00 |
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Thien TranandShengqi Chen
|
11f88260a2
|
[Kimi-K3] Migrate FlashKDA to PyTorch stable ABI (#50818)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Shengqi Chen <harry-chen@outlook.com>
|
2026-08-03 17:18:08 -07:00 |
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Thien TranandCodex
|
34bb795ff3
|
[CI] Add M3 MSA tests to CI (#49143)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Codex <noreply@openai.com>
|
2026-07-31 01:01:48 -07:00 |
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Thien Tran
|
61ac368021
|
[Kimi-K3] Add AttnRes kernels (#50090)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-07-28 00:22:09 -07:00 |
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Thien TranandCodex
|
b44311b6ef
|
[CI] stabilize GDN prefill CuTeDSL test (#49388)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Codex <noreply@openai.com>
|
2026-07-22 09:03:46 -07:00 |
|
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Thien Tran
|
2730b657c4
|
[Bugfix] Fix broken NVVM caused by CuteDSL 4.6.0 (#49108)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-07-19 19:45:56 -07:00 |
|
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Thien Tran
|
fe784ff22e
|
[M3] Improve indexer for long-context decode (sm100) (#48582)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-07-16 18:12:15 -07:00 |
|
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Thien Tran
|
85e296950c
|
BF16x3 router GEMM (#47973)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-07-16 17:04:20 +08:00 |
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Thien Tran
|
0d2f4e7c9c
|
Allow FlashInfer A2A backends for TRTLLM FP8 MoE Modular (#46661)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-07-08 14:58:39 -07:00 |
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Thien Tran
|
e7b3853bac
|
Remove router weight upcast for DSv2-related models (#47970)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-07-08 11:19:10 +00:00 |
|
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Thien Tran
|
43916891b2
|
[GDN] Improve kkt kernel of CuteDSL prefill backend (#46346)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-06-29 18:34:18 -07:00 |
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Thien TranandYongye Zhu
|
4c62663315
|
[M3] Enable FP8 sparse GQA (#45744)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Yongye Zhu <zyy1102000@gmail.com>
|
2026-06-16 21:38:03 -07:00 |
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|
Thien Tranandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
5bdc01bcc3
|
[M3] Tune Triton indexer score decode for spec-decode (#45743)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
2026-06-16 21:07:34 -07:00 |
|
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Thien Tran
|
b2cfae777d
|
Add Triton recompile detection (#45631)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-06-16 18:25:28 +08:00 |
|
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Thien Tran
|
d2889722ff
|
[Bugfix] Corrupted MLA + linear attention (#43961)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-05-29 05:00:51 -07:00 |
|
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Thien Tran
|
e54eff769d
|
[Bugfix] Pass routed_scaling_factor to FlashInfer TRTLLM BF16 MoE (#43769)
|
2026-05-27 21:29:14 -07:00 |
|
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Thien Tran
|
d56612c621
|
[GDN] GDN Prefill kernel for SM100 (#43273)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-05-26 14:02:11 +08:00 |
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Thien TranandYongye Zhu
|
724ed2fc35
|
[DSv4] Improved dequant gather K cache kernel (#42236)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Yongye Zhu <zyy1102000@gmail.com>
|
2026-05-11 10:41:12 -04:00 |
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Thien Tran
|
530d371302
|
[DSv4] Improved fused Indexer Q quant kernel (#41428)
|
2026-05-09 01:20:32 -07:00 |
|
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Thien Tran
|
296741d025
|
[DSv4] Use cvt PTX for FP32->FP4 conversion (#41015)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2026-04-29 16:16:40 -07:00 |
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Thien Tran
|
a0933c3bd6
|
[Bugfix] Enable FP8 KV cache for FlashInfer and Triton backend on non-sm100 GPUs (#24577)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2025-09-10 12:33:41 -07:00 |
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Thien Tran
|
2edc87b161
|
[Bugfix] Fix cache block size calculation for CPU MLA (#15848)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2025-04-02 01:45:02 -07:00 |
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Thien Tran
|
2039c6305b
|
[Bugfix] Fix imports for MoE on CPU (#15841)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2025-04-02 03:33:55 +00:00 |
|
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Thien Tran
|
4f044b1d67
|
[Kernel][CPU] CPU MLA (#14744)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2025-03-25 09:34:59 +00:00 |
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Thien Tran
|
27b50f1fe6
|
[Bugfix][Kernel][CPU] Fix num_tokens in CPU rotary embedding kernel (#14667)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2025-03-13 23:47:49 -07:00 |
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Thien Tran
|
95d680b862
|
[Bugfix][IPEX] Add VLLM_CPU_MOE_PREPACK to allow disabling MoE prepack when CPU does not support it (#14681)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
|
2025-03-13 20:43:18 -07:00 |
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