 Misha GoinandClaude
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d79b52b182
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[Misc] Consolidate csrc shared headers and prune dead code (#60721)
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-10-12 09:46:22 -07:00 |
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Rehan KhanandBob
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fd0216d3b5
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[Bugfix][CPU] Fix fused Gumbel-max wrapping-window bias (#60221)
Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com>
Co-authored-by: Bob <bob@ibm.com>
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2026-10-08 15:15:53 +08:00 |
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Mia Ojeda
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3313825983
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[Bugfix][DiffusionGemma] Read the causal mask as int32 and compile the sample step (#59992)
Signed-off-by: ojeda-e <eojeda@league.com>
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2026-10-06 19:25:51 +08:00 |
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6660926d92
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[Bugfix][CPU] Fix macOS build on Apple Clang < 17: structured binding… (#58932)
Signed-off-by: Miajan Chowdhury <chowdhurymiajan@gmail.com>
Co-authored-by: Miajan Chowdhury <chowdhurymiajan@gmail.com>
Co-authored-by: Robert Shaw <114415538+robertgshaw2-redhat@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-10-02 10:01:07 +08:00 |
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almayneandLi, Jiang <jiang1.li@intel.com>
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93dd80f636
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[CPU] Conv1d optimised kernel for aarch64 (#54093)
Signed-off-by: Anna Mayne <anna.mayne@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-09-30 20:23:42 +08:00 |
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Rukhaiya2004andLi, Jiang <jiang1.li@intel.com>
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72e7874fa6
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[Hardware][Power] Enable W4A16 (AWQ & GPTQ) quantization on POWER10 using VSX (#59149)
Signed-off-by: Rukhaiya <bibirukhaiya123@gmail.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-09-30 19:44:48 +08:00 |
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Rehan KhanandLi, Jiang <jiang1.li@intel.com>
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583637f126
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[CPU][Perf] Add vectorized Sampler Kernel (#53913)
Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-09-30 15:16:28 +08:00 |
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f34a0e0797
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[CPU] Gate the AVX10.2 paths on compiler support (#58133)
Signed-off-by: R <Ganesh.R@amd.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-09-24 18:07:53 +08:00 |
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Ankit-Jaiswal-AMDandDouglas Lehr
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88afb9dcac
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[CPU] Adds support for fp32 attention sinks (#56252)
Signed-off-by: Ankit Jaiswal <ankit.jaiswal@amd.com>
Co-authored-by: Douglas Lehr <91553416+dllehr-amd@users.noreply.github.com>
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2026-09-23 08:55:09 -05:00 |
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Wentao Ye
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4868312128
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[Refactor] Remove dead kernel code (#57621)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
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2026-09-20 10:39:23 -07:00 |
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92b40f5a14
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[CPU][Perf] refactor paged attention for Arm CPUs (#56045)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: Codex <noreply@openai.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-09-20 12:25:13 +08:00 |
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Yuwen ZhouandLi, Jiang <jiang1.li@intel.com>
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b346479065
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[CPU] Add CPU FP8 W8A8 linear/MoE support (#49942)
Signed-off-by: yuwenzho <yuwen.zhou@intel.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-09-18 17:59:42 +08:00 |
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117cf43fb6
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[HARDWARE][POWER] Enable W8A8 INT8 MoE on POWER (#55316)
Signed-off-by: Rukhaiya <bibirukhaiya123@gmail.com>
Signed-off-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Antigravity <antigravity@google.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-09-17 21:45:13 +08:00 |
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Harry MellorandClaude Opus 5
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8c1557a79c
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Add pydocstyle to the ruff rules (#52136)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
Signed-off-by: Harry Mellor <hej.mellor@gmail.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-09-16 16:44:29 +00:00 |
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Fadi ArafehandLi, Jiang <jiang1.li@intel.com>
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e3f755b732
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[CPU] Speedup LM Head on Arm CPUs (#55352)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-09-11 16:21:14 +08:00 |
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Li, Jiang
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c3ccc0e957
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[Model] Add DeepSeek-V4 CPU backend (#55355)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-09-10 14:14:48 +08:00 |
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Roderick Wuandmgoin
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2c9d68f80b
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[Quant][Kernel] Remove GPTQ Group/Dynamic Activation Ordering (#54809)
Signed-off-by: Roderick-Wu <roderickwu2003@gmail.com>
Signed-off-by: Roderick Wu <roderickwu2003@gmail.com>
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: mgoin <mgoin64@gmail.com>
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2026-09-08 12:45:12 -07:00 |
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zhao, zhenhui
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1c344ed41e
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[CPU] [Feat] Add native AMX-FP8 attention impl for Diamond Rapids (#49410)
Signed-off-by: zhejiangxiaomai <zhenhui.zhao@intel.com>
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2026-09-06 11:06:56 +08:00 |
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Li, Jiang
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8340fe1bb9
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[CI/Build] Fix flaky failures in CPU CI image building (#55317)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-09-04 20:27:02 +08:00 |
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Tianmu LiandOpenAI Codex
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c6c33f2b1f
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[CPU] Support FP16/BF16 persisted GDN state on AMX (#52191)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: OpenAI Codex <noreply@openai.com>
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2026-08-31 16:32:20 +08:00 |
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Li, Jiang
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fdbf2ddbd2
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[Bugfix][CPU] Fix several bugs (#54042)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-08-31 15:33:06 +08:00 |
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Li, Jiang
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e4d61d0d22
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[CPU] Add AMX-only high-performance MLA backend for DeepSeek V2/V3/R1 (#52616)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-08-19 10:28:52 +08:00 |
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ccaadaroandLi, Jiang <jiang1.li@intel.com>
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bda4c3e8ee
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[CPU] Fold the MXFP4 block scale in 2 instructions instead of 4 (#51583)
Signed-off-by: ccaadaro <ccanadar@unex.es>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-08-14 08:19:21 +00:00 |
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velonica0andLi, Jiang <jiang1.li@intel.com>
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ac7509e2b1
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[Bugfix][CPU][RISC-V] Fix build: make FP32Vec copy constructors non-explicit (#51099)
Signed-off-by: velonica0 <like@mail.nankai.edu.cn>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-08-14 04:59:01 +00:00 |
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61826c1c6f
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[Hardware][Power] Unqualized MoE Backend for Power (VSX) (#51624)
Signed-off-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Antigravity <antigravity@google.com>
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2026-08-13 10:56:09 +08:00 |
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Rehan KhanandLi, Jiang <jiang1.li@intel.com>
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b22afe45ac
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[CPU] Enable GPTQ and AWQ quantization for s390x (#51148)
Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-08-10 11:41:43 +08:00 |
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Tianmu Li
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700d39b558
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[CPU] Optimize routed FP8/MXFP4 MoE GEMM dispatch (#50949)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
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2026-08-08 12:56:14 +08:00 |
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Wentao Ye
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c84789c40b
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[Refactor] Remove kernel dead code (#51051)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
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2026-08-07 01:20:19 -07:00 |
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maobaolongandLi, Jiang <jiang1.li@intel.com>
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13726c80fe
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[CPU] Add MLA backend so DeepSeek-V2/V3 can run on CPU (#49453)
Signed-off-by: baoloongmao <baoloongmao@tencent.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-08-06 16:51:41 +08:00 |
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Harjoth Khara
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122b3d46b6
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[Bugfix][CPU] Fix macOS build: std::sqrt is not constexpr under libc++ (#50915)
Signed-off-by: harjoth <harjoth.khara@gmail.com>
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2026-08-04 14:56:33 +00:00 |
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0a6446005d
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[CPU] Migrate unquantized MoE to the modular-kernel experts structure (#50133)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Fadi Arafeh <fadi.arafeh@arm.com>
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2026-08-03 14:55:04 +08:00 |
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Rehan KhanandLi, Jiang <jiang1.li@intel.com>
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88bc8fb56f
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[CPU][s390x] Optimize inference perf and add oneDNN INT8 GEMM for s390x (#50219)
Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-07-31 17:49:31 +08:00 |
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Li, JiangandClaude
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072a472782
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[CPU] Bump up CPU kernels to latest version (#50387)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-07-30 19:18:43 +08:00 |
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65a1a16594
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[CPU] Fix FP8 attention scratchpad sizing (#50194)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: Codex <noreply@openai.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-07-29 15:34:37 +08:00 |
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Rehan KhanandLi, Jiang <jiang1.li@intel.com>
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db7a79cbf7
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[CPU] Fix s390x builds and update torch version in dockerfile (#50144)
Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-07-29 12:52:17 +08:00 |
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544cb724c8
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[CPU][Spec Decode] Optimize GDN conv path for speculative decoding (#48577)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: Codex <codex@openai.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-07-27 06:20:14 +00:00 |
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Fadi ArafehandLi, Jiang <jiang1.li@intel.com>
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c314af1abf
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[CPU][Perf] INT8 Fused MoE Kernel for Arm CPUs (#48637)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-07-27 05:53:09 +00:00 |
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Akash kaothalkarandAkash kaothalkar
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f19ee27e39
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[Hardware][Power] Add FAST_EXP for Power (#49571)
Signed-off-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
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2026-07-27 05:47:29 +00:00 |
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SyaandLi, Jiang <jiang1.li@intel.com>
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5b3762a7f0
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[Bugfix][CPU] Fix Clang OpenMP build on macOS (#49021)
Signed-off-by: markyangcc <mmdou3@163.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-07-21 09:58:52 +00:00 |
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5c9f6557d7
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[Hardware][CPU] Enable granite-4 model on cpu (#47641)
Signed-off-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com>
Signed-off-by: Akash Kaothalkar <akashkaothalkar@dhcp-9-123-5-76.bl1-in.ibm.com>
Signed-off-by: Akash Kaothalkar <akashkaothalkar@Akashs-MBP.lan>
Signed-off-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Akash Kaothalkar <akashkaothalkar@dhcp-9-123-5-76.bl1-in.ibm.com>
Co-authored-by: Akash Kaothalkar <akashkaothalkar@Akashs-MBP.lan>
Co-authored-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com>
Co-authored-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-07-20 06:15:16 +00:00 |
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Michael Goin
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0b54201a04
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[CI] Build macOS arm64 CPU wheel natively on the macmini queue (#48289)
Signed-off-by: mgoin <mgoin64@gmail.com>
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2026-07-14 19:40:26 +00:00 |
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05fa8183a6
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[CPU][Spec Decode] Support DFlash speculative decoding for GDN models on CPU (#46090)
Signed-off-by: guybd <guy.boudoukh@intel.com>
Signed-off-by: Guy Boudoukh <guy.boudoukh@intel.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-07-13 04:16:18 +00:00 |
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c85d72076a
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[HARDWARE][POWER] optimize math functions of VSX power (#47321)
Signed-off-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com>
Signed-off-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
Signed-off-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Signed-off-by: Rukhaiya <bibirukhaiya123@gmail.com>
Co-authored-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com>
Co-authored-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
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2026-07-07 09:35:47 +00:00 |
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Li, Jiang
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344609ab17
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[CI/Build] Fix pre-commit check (#47695)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-07-06 08:24:24 +00:00 |
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velonica0
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990c2a0187
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[RISC-V] Enable BF16 on VLEN=256 hardware (#45243)
Signed-off-by: velonica0 <like@mail.nankai.edu.cn>
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2026-07-06 06:05:16 +00:00 |
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LiuTongandClaude
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e433634c78
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[Performance][Hardware][RISC-V] Reduce LMUL pressure in INT4 LUT dequant (#47538)
Signed-off-by: liutong <liutong@iscas.ac.cn>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-07-06 05:58:56 +00:00 |
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LiuTongandClaude
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16f8110935
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[Bugfix][CPU][RISC-V] Fix VLEN detection for RVV attention path (#47532)
Signed-off-by: liutong <liutong@iscas.ac.cn>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-07-06 05:58:03 +00:00 |
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Fadi Arafeh
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f1073c050c
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[CPU][BugFix] Multiple fixes to w4a8_int8 CPU MoE path (#46739)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
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2026-07-06 05:39:20 +00:00 |
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gausah01
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26eb87204d
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[Bugfix] Fix CPU split-KV scratchpad sizing (#45844)
Signed-off-by: Gauri Sahnan <gauri.sahnan@arm.com>
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2026-07-04 06:47:23 +00:00 |
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almayneandLi, Jiang <jiang1.li@intel.com>
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89e99202f2
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[CPU][Perf]Added tanh AOR for faster gelu activations. (#44639)
Signed-off-by: Anna Mayne <anna.mayne@arm.com>
Signed-off-by: almayne <anna.mayne@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-06-30 23:24:40 -07:00 |
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