 Chaojun Zhangandvllm-agent
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074c83a09a
|
[CI][Intel] Skip ROCm-only test_topk_gating_enabled_by_cdna on XPU (#61932)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: vllm-agent <claw@inferact.ai>
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2026-10-16 13:44:32 +08:00 |
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85c94c1706
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[Tests][XPU] Skip modelopt_fp4 online MoE re-quantization test on XPU (#61723)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kevin H. Luu <khluu000@gmail.com>
Co-authored-by: Cyrus Leung <tlleungac@connect.ust.hk>
|
2026-10-15 00:23:45 -07:00 |
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Chaojun ZhangandKevin H. Luu
|
ab593678b5
|
[CI][XPU] Ignore test_reload.py on Intel CI (#61740)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kevin H. Luu <khluu000@gmail.com>
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2026-10-15 15:03:34 +08:00 |
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|
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b337523c11
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[XPU] [Test] Extend spawn-safe sitecustomize monkeypatch to XPU (#57911)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
Co-authored-by: xiangdong <40376367+zxd1997066@users.noreply.github.com>
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2026-10-13 13:12:10 +08:00 |
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Chaojun Zhang
|
b027ac8312
|
[XPU] Support register KV offload mmap region as pinned host memory on XPU (#51956)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
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2026-10-09 18:58:07 +08:00 |
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Chaojun Zhang
|
dfaabf91ac
|
[XPU] [CI] Fix stale ignore path for weight_transfer_metrics tests on Intel CI (#60558)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
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2026-10-08 17:48:47 +08:00 |
|
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Chaojun ZhangandKunshang Ji
|
aba01ef1f7
|
[XPU][CI] Skip test_core_engine_actor_manager.py on Intel CI (#59338)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-09-30 13:23:02 -05:00 |
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Chaojun ZhangandKunshang Ji
|
02a3c6dfc5
|
[Test] Skip IPC weight-transfer test on XPU platforms (#59379)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-09-30 21:50:40 +08:00 |
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Chaojun Zhang
|
7230dfea50
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[XPU] Preserve non-contiguous strides when pinning CPU tensors for UVA view (#54874)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
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2026-09-29 09:43:07 +08:00 |
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Chaojun ZhangandCopilot
|
1fee69838e
|
[XPU] Fix Nemotron FP8 LM-eval config: drop CUDA-only moe_backend and wire to new Buildkite job (#49685)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
|
2026-09-22 10:05:26 +08:00 |
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Chaojun ZhangandKunshang Ji
|
db7f1f6714
|
[CI][XPU] Deselect Ray UT in XPU V1 test Job (#57889)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-09-21 20:54:58 +08:00 |
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Chaojun ZhangandKunshang Ji
|
622934e61f
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[XPU] Honor device_ids for worker device placement (#56015)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-09-16 11:53:23 +08:00 |
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Chaojun Zhang
|
39545e475d
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Revert "[CI][XPU] Disable model runner V2 for XPU quantization test for some partially pre-quantized models" (#56394)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-09-14 11:40:13 +08:00 |
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Chaojun Zhang
|
5c0aeb5954
|
[CI][XPU] Disable model runner V2 for XPU quantization test for some partially pre-quantized models (#56179)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-09-10 11:02:57 +08:00 |
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Chaojun Zhang
|
8648446515
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[XPU][LoRA] Support LoRA for DeepSeek V4 on XPU (#53689)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-09-07 17:44:12 +08:00 |
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Chaojun Zhang
|
392db567b2
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[CI] [Test] skip test_wna16_cuda_high_bit_skips_humming on non-CUDA platforms (#55660)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-09-07 16:57:15 +08:00 |
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Chaojun Zhang
|
f485081e8b
|
[XPU] Support EC connector KV Offloading on XPU (#49532)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-08-19 10:25:23 +08:00 |
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Chaojun Zhang
|
8c011da6d0
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[XPU] Route block-quantized FP8 weights to the W8A8 kernel (#50787)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-08-12 16:57:22 +08:00 |
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Chaojun Zhang
|
f863387250
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[XPU] Fix UVA weight offloading (non-pinned-tensor views and static Triton launcher) (#51770)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-08-11 21:48:44 +08:00 |
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Chaojun Zhang
|
b706fd1628
|
[CI][XPU] Work around intermittent segfault in Intel XPU CI with VLLM_DISABLE_COMPILE_CACHE=1 (#51337)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-08-07 05:18:25 +00:00 |
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Chaojun ZhangandKunshang Ji
|
276f0bb5c1
|
[XPU] Register fake meta kernel for fp4_gemm (#50946)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-08-06 17:18:42 +08:00 |
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Chaojun ZhangandKunshang Ji
|
482cfc20f0
|
[XPU] Unify XPU RMSNorm kernels with vllm_c and drop redundant XPU-specific implementation (#46981)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-07-31 17:28:18 +08:00 |
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Chaojun ZhangandKunshang Ji
|
bf4f633b4c
|
[XPU] Enable QK Norm + RoPE fusion pass on XPU (#49394)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-07-27 03:22:29 +00:00 |
|
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Chaojun Zhangandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
0231dd5467
|
[BugFix][LoRA] Skip marlin-backend gpt-oss LoRA tests on XPU (#49385)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
2026-07-24 09:16:00 +08:00 |
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Chaojun Zhang
|
5811ed6a05
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[Test][kv_offload] Fix flaky drain() helper in test_fs_tier.py (#48545)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-07-15 14:53:47 +03:00 |
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Chaojun Zhang
|
28eaf05d56
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[XPU] Enable v1/sample tests on XPU CI (#44472)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-07-10 15:40:51 +08:00 |
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Chaojun Zhang
|
b8c7c86533
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[XPU][LoRA] Fix torch.compile DEVICE_LOST by avoiding view-mutation in LoRA shrink (#47944)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-07-09 06:08:30 +00:00 |
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Chaojun Zhang
|
440002552e
|
[XPU] [Fusion passes] Disable fuse_rope_kvcache_cat_mla & qk_norm_rope_ fusion on XPU (#47962)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-07-08 09:23:06 +00:00 |
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Chaojun Zhang
|
6569df6a3e
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[Test][LoRA] Use lightweight CPU reference and skip heavy cleanup in punica ops tests (#47534)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-07-06 11:29:59 +08:00 |
|
|
|
d2ec433e37
|
[XPU] Fix Eagle3 initialization on XPU (#43957)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-07-06 08:46:05 +08:00 |
|
|
Chaojun ZhangandCopilot
|
1a308c449c
|
[XPU] Add W8A8 FP8 linear kernel with multi-granularity quant support (#43645)
Signed-off-by: Chaojun,Zhang <chaojun.zhang@intel.com>
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
|
2026-07-04 18:10:01 +08:00 |
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Chaojun Zhang
|
8357226f4f
|
[XPU][CI] Split test_punica_ops into separate pytest invocations for stability (#47376)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-07-02 07:50:55 +00:00 |
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Chaojun Zhang
|
13c49f9845
|
[xpu][lora]: Align LoRA implementation with Punica GPU: fix _apply_expand rank mismatch, add_inputs hardcode, and MoE EP (#45368)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-07-01 22:14:04 +08:00 |
|
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Chaojun Zhang
|
ea9ddf59fc
|
[XPU][CI] Enable shared loader test (#45977)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-06-30 11:20:33 +00:00 |
|
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Chaojun Zhang
|
8cc242335d
|
[XPU] Optimize XPU worker shutdown logic to prevent resource leak (#46433)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-06-30 15:27:21 +08:00 |
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Chaojun Zhang
|
06e1e0885c
|
[XPU] Fix test_logprobs_e2e import error: pin lm-eval[api]>=0.4.12 (#44469)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-06-17 12:26:47 +00:00 |
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Chaojun ZhangandKunshang Ji
|
556b063e45
|
[XPU] Fix test_spec_decode_logprobs: use FLASH_ATTN for XPU in GPU_DETERMINISM_KWARGS (#44468)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-06-17 11:07:04 +08:00 |
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Chaojun Zhang
|
2725c84aae
|
[XPU] Enable sequence parallel support for XPU (#38608)
Signed-off-by: chaojun-zhang <chaojun.zhang@intel.com>
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Signed-off-by: Chaojun,Zhang <chaojun.zhang@intel.com>
|
2026-06-14 19:26:46 -07:00 |
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|
Chaojun Zhang
|
fa662b1a8b
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[XPU] Cap topk/topp Triton BLOCK_SIZE to 4096 to fix Top-p mask difference failures (#44470)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-06-08 09:36:51 +00:00 |
|
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Chaojun Zhang
|
810966453a
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[XPU] Support cpu kv offloading and tiering offloading on XPU platform (#36423)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-06-07 09:59:28 +08:00 |
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Chaojun ZhangandKunshang Ji
|
a3a5a5ece5
|
[XPU][Bugfix] Fix per_token_group_fp8_quant missing dummy args on XPU (#43930)
Signed-off-by: Chaojun,Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-06-02 03:09:21 +00:00 |
|
|
Chaojun Zhang
|
bd0aecdc08
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[XPU][CI] Fix test_audio_in_video flake by using module-scoped server fixture (#44146)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
|
2026-06-01 11:21:36 +00:00 |
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Chaojun Zhang
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861b97765d
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[XPU] Fix fused MoE LoRA kernel crash on XPU by using platform-agnos num_compute_units (#43646)
Signed-off-by: Chaojun,Zhang <chaojun.zhang@intel.com>
|
2026-05-26 03:40:32 -07:00 |
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|
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71d810bbf4
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[XPU] Ensure RNG offset alignment with PyTorch requirements in XPU sampler (#43028)
Signed-off-by: chaojun-zhang <chaojun.zhang@intel.com>
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
2026-05-26 02:01:30 +00:00 |
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|
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f1e3f0e6d6
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[XPU] Use custom op collective behavior (#41354)
Signed-off-by: Chaojun,Zhang <chaojun.zhang@intel.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-05-19 14:14:59 +08:00 |
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Chaojun Zhang
|
19df11f5d1
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[CI][XPU]Ignore some lora tests from LoRA Intel CI pipeline (#42010)
Signed-off-by: chaojun-zhang <chaojun.zhang@intel.com>
|
2026-05-08 17:34:27 +08:00 |
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Chaojun Zhangandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
2a84da3b17
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[XPU] Implement out-of-place all-reduce functionality (#41808)
Signed-off-by: Chaojun,Zhang <chaojun.zhang@intel.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
2026-05-07 05:58:05 -07:00 |
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Chaojun Zhang
|
805e9f7b77
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[XPU] Fix lora bugs & enable UTs under tests/lora (#38206)
Signed-off-by: chaojun-zhang <chaojun.zhang@intel.com>
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2026-05-07 05:58:00 -07:00 |
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Chaojun ZhangandKunshang Ji
|
1c58876618
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[XPU] Disable CUDA graph memory estimate on XPU platform (#41344)
Signed-off-by: chaojun-zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-05-06 16:38:18 +08:00 |
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Chaojun ZhangandKunshang Ji
|
ccaf5ffaa3
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[XPU] disable fusion pattern support on XPU platform (#39789)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-04-23 10:07:45 +08:00 |
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Chaojun ZhangandKunshang Ji
|
4f4713f96e
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[XPU] [torch.compile] Skipping CUDA graph memory estimation to avoid startup errors. (#39977)
Signed-off-by: chaojun-zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-04-20 13:04:39 +08:00 |
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Chaojun Zhangandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
993859ceb0
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[XPU] fix all_reduce all-zero accuracy issue under torch.compile (#39844)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-04-18 02:33:07 +00:00 |
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Chaojun Zhang
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82f836d976
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[XPU] Support LoRA via torch.compile on XPU platform (#36962)
Signed-off-by: chzhang <chaojun.zhang@intel.com>
|
2026-03-13 10:34:59 +00:00 |
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Chaojun ZhangandKunshang Ji
|
9f9a675b23
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[XPU][8/N] Fix kernel bugs in XPU LoRA and MOE LORA (#34115)
Signed-off-by: chzhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
|
2026-02-26 15:46:44 +08:00 |
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Chaojun Zhang
|
a4730c1b4f
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[XPU]Fix crash due to removed VLLM_USE_V1 attribute (#28520)
Signed-off-by: chaojun-zhang <chaojun.zhang@intel.com>
|
2025-11-12 10:20:55 +00:00 |
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Chaojun Zhang
|
7dbe6d81d6
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Fix Fused MoE LoRA Triton kernel bug (#28450)
Signed-off-by: chaojun-zhang <chaojun.zhang@intel.com>
|
2025-11-11 20:46:47 +08:00 |
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Chaojun Zhang
|
3bc18127ff
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[XPU] Whisper model support on XPU Platform (#25123)
Signed-off-by: chzhang <chaojun.zhang@intel.com>
|
2025-09-18 04:30:10 +00:00 |
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Chaojun Zhang
|
862f2ef893
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[XPU] Fix the bug of LoRA logits on the XPU platform (#24081)
Signed-off-by: chzhang <chaojun.zhang@intel.com>
|
2025-09-03 08:21:18 +08:00 |
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Chaojun Zhang
|
235c9db8a7
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[XPU] support data parallel for MoE models on XPU (#22887)
Signed-off-by: chzhang <chaojun.zhang@intel.com>
|
2025-08-29 09:23:04 +08:00 |
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Chaojun Zhang
|
8a044754bd
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[XPU] Delay BF16 check to worker init for spawn compatibility (#22979)
Signed-off-by: chzhang <chaojun.zhang@intel.com>
|
2025-08-25 13:09:26 -07:00 |
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Chaojun ZhangandJee Jee Li
|
ec261b0291
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[XPU] IPEX-optimized Punica Wrapper on XPU (#21703)
Signed-off-by: chzhang <chaojun.zhang@intel.com>
Co-authored-by: Jee Jee Li <pandaleefree@gmail.com>
|
2025-07-28 16:43:37 +00:00 |
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Chaojun Zhang
|
d9f9a3fd96
|
[XPU] Conditionally import CUDA-specific passes to avoid import errors on xpu platform (#21036)
Signed-off-by: chzhang <chaojun.zhang@intel.com>
|
2025-07-24 23:23:36 +08:00 |
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Chaojun Zhang
|
25d585ab7b
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[XPU] Enable external_launcher to serve as an executor via torchrun (#21021)
Signed-off-by: chzhang <chaojun.zhang@intel.com>
|
2025-07-21 21:47:35 -07:00 |
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