 Li, Jiang
|
9adba10f3f
|
[Bugfix] Fix pre-commit check (#60840)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-10-09 12:48:32 +00:00 |
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|
Li, Jiang
|
b44895cf93
|
[CPU] Use pre-built triton (#58140)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-09-24 16:12:34 +08:00 |
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|
Li, Jiang
|
b68408043d
|
[Bugfix][CPU] Add per-tensor FP8 W8A16 kernel to fix Ministral crash on CPU (#56985)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-09-16 15:49:17 +08:00 |
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|
Li, Jiang
|
79f0be21ff
|
[Bugfix][CPU] Fix DeepSeek-R1 (FP8 MLA + MoE) correctness on CPU backend (#56773)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-09-14 17:30:28 +08:00 |
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|
Li, Jiang
|
46bae7e98c
|
[CI/Build][CPU] Fix flaky rust downloads, broken prune flag, and triton-cpu cache coupling (#56247)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-09-10 22:27:26 +08:00 |
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|
Li, Jiang
|
c3ccc0e957
|
[Model] Add DeepSeek-V4 CPU backend (#55355)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-09-10 14:14:48 +08:00 |
|
|
Li, Jiang
|
8340fe1bb9
|
[CI/Build] Fix flaky failures in CPU CI image building (#55317)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-09-04 20:27:02 +08:00 |
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|
Li, Jiang
|
fdbf2ddbd2
|
[Bugfix][CPU] Fix several bugs (#54042)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-08-31 15:33:06 +08:00 |
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|
Li, Jiang
|
e4d61d0d22
|
[CPU] Add AMX-only high-performance MLA backend for DeepSeek V2/V3/R1 (#52616)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-08-19 10:28:52 +08:00 |
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|
Li, Jiang
|
1c3633acaf
|
[CI/Build][CPU] Shrink triton-cpu-build layer by dropping build artifacts (#52127)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-08-13 17:17:00 +08:00 |
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Li, Jiang
|
373592ef57
|
[CPU] Ship triton-cpu wheel and fix several hardcoded pin_memory=True (#52092)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-08-13 14:40:53 +08:00 |
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|
Li, Jiang
|
6accb779a3
|
[CI] Add registry layer cache to x86 CPU image build (#51911)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-08-12 17:58:01 +08:00 |
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|
Li, Jiang
|
7ce84b99ce
|
[CPU] Restore linear dispatch for small unquantized GEMMs (#51379)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-08-10 11:29:59 +08:00 |
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|
Li, Jiang
|
c8602c7906
|
[CPU] Refine CPU kernel dispatch (#50801)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-08-03 17:42:53 +08:00 |
|
|
|
0a6446005d
|
[CPU] Migrate unquantized MoE to the modular-kernel experts structure (#50133)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Fadi Arafeh <fadi.arafeh@arm.com>
|
2026-08-03 14:55:04 +08:00 |
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|
Li, JiangandClaude
|
072a472782
|
[CPU] Bump up CPU kernels to latest version (#50387)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Co-authored-by: Claude <noreply@anthropic.com>
|
2026-07-30 19:18:43 +08:00 |
|
|
Li, Jiang
|
90245f4190
|
[Bugfix] Fix multi-modal support on CPU MRV2 (#50073)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-07-28 06:09:48 +00:00 |
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|
Li, JiangandClaude Sonnet 5
|
eb290ab673
|
[Bugfix][CPU] Zero-pad MoE intermediate size for grouped-gemm TP alignment (#49591)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Co-authored-by: Claude Sonnet 5 <noreply@anthropic.com>
|
2026-07-27 16:32:23 +08:00 |
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|
Li, Jiang
|
1171467e91
|
[CPU] Fix Qwen-Next SSM type for AMX GDN (#48073)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-07-09 15:09:31 +08:00 |
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|
Li, Jiang
|
344609ab17
|
[CI/Build] Fix pre-commit check (#47695)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-07-06 08:24:24 +00:00 |
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|
Li, Jiang
|
e9cc1fd093
|
[CI/Build][CPU] Remove global extra index (#47687)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-07-06 13:42:01 +08:00 |
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|
Li, JiangandHarry Mellor
|
14f8660a18
|
[CI/Build] Add CPU test dependency pre-commit hooks (#47032)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
Co-authored-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
|
2026-06-30 07:59:13 +00:00 |
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|
Li, Jiang
|
abc71548ef
|
[CI/Build][CPU] Add test image cache clean-up (#46831)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-06-26 23:28:49 +08:00 |
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Li, Jiangandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
92221485aa
|
[CPU][CI/Build] Allow more CPU CI agents (#46702)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
2026-06-25 19:33:39 +08:00 |
|
|
Li, Jiang
|
1c7bc18318
|
[Bugfix][CPU] Fix CPU model runner v2 (#46365)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-06-22 22:52:05 +08:00 |
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|
Li, Jiang
|
a7fdfeef72
|
[CPU] Support Gemma Diffusion (#45690)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-06-16 14:39:56 +08:00 |
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|
Li, Jiang
|
8760f972ca
|
[CPU] Refine CPU attention frontend (#45391)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-06-14 19:26:54 -07:00 |
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|
Li, Jiang
|
980796cd07
|
[CI/Build][CPU] Fix flaky CI image build failure and unexpected warnings (#44852)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-06-08 11:10:06 +00:00 |
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|
Li, Jiang
|
c505cd93ef
|
[CI/Build] Disable CPU-Compatibility Tests (#44605)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-06-05 13:14:26 +08:00 |
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|
Li, Jiang
|
823d271c0d
|
[Attention][CPU] Standardize kv layout to blocks first (#44393)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-06-03 19:03:09 +08:00 |
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|
Li, Jiang
|
3f6f508e14
|
[Bugfix][CPU] Remove invalid extra deps (#43977)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-05-29 22:02:09 +08:00 |
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|
Li, Jiang
|
20d69d100a
|
[CPU] Migrate cpu_awq into awq_marlin (#43841)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-05-28 22:36:31 +08:00 |
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Li, Jiang
|
65b7a812a2
|
[CPU] Experimentally enable Triton and MRV2 (#43225)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-05-22 01:48:17 -07:00 |
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Li, Jiang
|
b4601ad43f
|
[CPU] Add fused GDN support for AMX CPU platform (#42707)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-05-18 03:04:36 -07:00 |
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Li, Jiang
|
95cfe102a5
|
[Bugfix] Ensure embeding model compilation on CPU (#42709)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-05-15 18:58:19 +08:00 |
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Li, Jiang
|
b3945cc316
|
[CPU] Bump up to the latest CPU kernels (#41924)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-05-07 05:45:59 -07:00 |
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Li, Jiang
|
d02421a7db
|
[CPU] Refactor CPU affinity and memory management (#39781)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-04-17 21:01:08 +08:00 |
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|
Li, Jiang
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324a3d2bd8
|
[CI/Build] Improve stability of CPU tests (#39966)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-04-16 21:50:36 +08:00 |
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Li, Jiang
|
eb92ba740a
|
[CI/Build] Fix sentence-transformers version in CPU test (#39557)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-04-11 07:04:25 +00:00 |
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Li, Jiang
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21d7ecc5b0
|
[CI/Build] Add audio deps in Dockerfile.cpu (#38876)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-04-03 05:05:14 +00:00 |
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Li, Jiang
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c6f722b93e
|
[CPU] Support gelu act in cpu_fused_moe (#38770)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-04-02 14:14:32 +08:00 |
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Li, Jiang
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36d7f19897
|
[CPU] Support head_size 512 in cpu_attn (#38676)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-04-01 05:42:27 +00:00 |
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Li, Jiang
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6557f4937f
|
[Bugfix][CPU] Skip set_num_threads after thread binding (#38535)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-03-30 20:13:00 +08:00 |
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Li, Jiang
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becaed6ec8
|
[CPU] Support CT W4A16 on CPU MP kernel (#38219)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-03-27 14:15:28 +08:00 |
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Li, Jiang
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352b90c4a4
|
[Bugfix] Add replacement of _compute_slot_mapping_kernel on CPU (#37987)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-03-24 07:00:20 -07:00 |
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Li, Jiang
|
3322e26420
|
[Bugfix] Avoid more OpenMP thread reallocation in CPU torch compile (#37538)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-03-19 10:24:39 +00:00 |
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Li, Jiang
|
261801242f
|
[Bugfix] Avoid OpenMP thread reallocation in CPU torch compile (#37391)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-03-18 07:51:39 +00:00 |
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Li, Jiang
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7362b4450a
|
[Bugfix] Avoid LD_PRELOAD check on MacOS (#37145)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-03-15 23:31:44 -07:00 |
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|
Li, Jiangandgemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
|
092ace9e3a
|
[UX] Improve UX of CPU backend (#36968)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Li, Jiang <bigpyj64@gmail.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
|
2026-03-14 09:27:29 +08:00 |
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Li, Jiang
|
217f27598d
|
[Bugfix] Avoid to replace non-tensor members in cpu model runner (#36430)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-03-09 13:06:28 +08:00 |
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|
Li, Jiang
|
440f0e7dc6
|
[Bugfix] Avoid src/dst as None in irecv/isend_tensor_dict (#35754)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-03-03 05:56:08 -08:00 |
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Li, Jiang
|
05339a7b20
|
[Bugfix][CPU] Fix llama4 inference on CPU (#34321)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-02-11 19:07:23 +08:00 |
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Li, Jiang
|
db6f71d4c9
|
[CI/Build] Fix CPU CI test case title (#33870)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-02-05 15:07:14 +08:00 |
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|
Li, Jiang
|
07daee132b
|
[CI/Build] Parallelize CPU CI tests (#33778)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2026-02-05 13:53:48 +08:00 |
|
|
Li, Jiangandgemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
|
8311f083bd
|
[Bugfix][CPU] Fix thread num for shared memory communication (#33317)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Li, Jiang <bigpyj64@gmail.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
|
2026-01-29 03:26:58 -08:00 |
|
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Li, Jiangandgemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
|
5da4c7d789
|
[CI/Build][CPU] Fix failed pooling tests and macos smoke test (#32907)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Li, Jiang <bigpyj64@gmail.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
|
2026-01-23 10:48:20 +00:00 |
|
|
Li, Jiangandgemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
|
8becf146bd
|
[Quantization][Refactor] Move CPU GPTQ kernel into MP linear (#31801)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Li, Jiang <bigpyj64@gmail.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
|
2026-01-06 19:10:18 +00:00 |
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Li, Jiang
|
7157596103
|
[CPU] Disable async schedule on CPU (#31525)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-12-30 12:34:08 +00:00 |
|
|
Li, Jiang
|
17347daaa2
|
[CI/Build][CPU] Update CPU CI test cases (#31466)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-12-29 14:17:52 +08:00 |
|
|
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420ba2dbb6
|
Enable aarch64 CPU performance benchmarks (#26494)
Signed-off-by: Ioana Ghiban <ioana.ghiban@arm.com>
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: Ioana Ghiban <ioana.ghiban@arm.com>
Co-authored-by: Fadi Arafeh <fadi.arafeh@arm.com>
|
2025-12-19 12:16:18 +00:00 |
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|
Li, Jiang
|
096b25c9ed
|
[Doc][CPU] Fix index link for CPU regular release wheels (#31015)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-12-19 07:29:52 +00:00 |
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|
Li, Jiang
|
f90d3636e2
|
[Bugfix][CPU] Fix Mac CPU build (#30955)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-12-18 01:38:22 -08:00 |
|
|
Li, Jiang
|
e3ab93c896
|
[CPU] Refactor CPU fused MOE (#30531)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-12-18 14:36:49 +08:00 |
|
|
Li, Jiangandgemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
|
cfb7e55515
|
[Doc][CPU] Update CPU doc (#30765)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Li, Jiang <bigpyj64@gmail.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
|
2025-12-18 04:59:09 +00:00 |
|
|
Li, Jiangandgemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
|
0cd5353644
|
[Bugfix][CPU] Fix CPU backend ROPE dispatch for VL models (#30829)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Li, Jiang <bigpyj64@gmail.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
|
2025-12-16 23:25:12 -08:00 |
|
|
Li, Jiang
|
9693dd0fe3
|
[CI/Build] Add x86 CPU wheel release pipeline (#28848)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-12-12 19:21:35 +00:00 |
|
|
Li, Jiang
|
e2f56c309d
|
[CPU] Update torch 2.9.1 for CPU backend (#29664)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-11-28 13:37:54 +00:00 |
|
|
Li, Jiang
|
882851dc81
|
[CI/Build][Bugfix] Fix auto label issues for CPU (#29610)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-11-27 14:51:26 +00:00 |
|
|
Li, Jiang
|
a5abd1d384
|
[CI] Auto label CPU related issues (#29602)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-11-27 11:33:19 +00:00 |
|
|
Li, Jiang
|
20852c8f4c
|
[CPU] Refactor CPU WNA16 (#28826)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-11-19 10:32:00 +08:00 |
|
|
Li, Jiang
|
577bb34fff
|
[CPU][Bugfix] Fix _to_list in CPU model runner (#28824)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-11-17 07:47:24 +00:00 |
|
|
Li, Jiang
|
7f829be7d3
|
[CPU] Refactor CPU attention backend (#27954)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-11-12 09:43:06 +08:00 |
|
|
Li, Jiang
|
eebf00cb0c
|
[Bugfix][CPU] Fix MRoPE dispatch on the CPU backend (#27800)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-10-30 15:12:05 +00:00 |
|
|
Li, JiangandIsotr0py
|
d34f5fe939
|
[Bugfix][CPU] Fallback oneDNN linear to torch linear to fix half gemm support on legecy platforms (#27526)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Co-authored-by: Isotr0py <mozf@mail2.sysu.edu.cn>
|
2025-10-27 23:25:44 -07:00 |
|
|
Li, Jiang
|
843af7f7fc
|
[Bugfix][CPU] Disable dual stream execution for experts on CPU (#27320)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-10-22 11:02:27 +00:00 |
|
|
Li, Jiang
|
5550ff9c25
|
[CI/Build] Update compressed tensor test path to fix CPU CI (#27068)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-10-16 22:34:56 -07:00 |
|
|
Li, Jiang
|
5c057e068f
|
[CPU] Refine batch reorder of CPU attention backend (#26096)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-10-04 21:54:35 +08:00 |
|
|
Li, Jiang
|
eb32335e35
|
[CPU] update torch 2.8 and fix missing fields in TorchSDPAMetadata (#25652)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-09-25 13:29:11 +00:00 |
|
|
Li, Jiang
|
1cbcfb94de
|
[Bugfix][CPU] Skip unsupported custom op register on CPU (#25534)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-09-24 06:21:51 +00:00 |
|
|
Li, Jiang
|
825fdb11ad
|
[Bugfix][CPU] Add placeholder to avoid import errors when using fused_moe ops on platforms without triton (#25137)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
|
2025-09-19 07:41:12 +00:00 |
|
|
Li, Jiang
|
8c1d4acbfe
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[CPU] Disable oneDNN linear on non-x86 platforms (#25166)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-09-19 07:27:22 +00:00 |
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Li, Jiang
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9fccd04e30
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[Bugfix] Fix Stream usage in CPU model runner and OneDNN kernel check (#25046)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-09-17 05:54:02 -07:00 |
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Li, Jiang
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59d5d2c736
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[CI/Build] Skip prompt embeddings tests on V1-only CPU backend (#24721)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-09-12 18:51:01 +08:00 |
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Li, Jiang
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7920de0a2a
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[Bugfix] Fix MRoPE dispatch on CPU (#24712)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-09-12 04:56:31 +00:00 |
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Li, Jiang
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29799ddacc
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[Bugfix] Add missing VIT backend dispatch on CPU (#24623)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-09-10 22:28:41 -07:00 |
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Li, Jiang
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57b1ce94f7
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[CPU] Refactor CPU unquantized linear (#24150)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-09-04 14:28:45 +08:00 |
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Li, Jiang
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ad39106b16
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[CPU] Enable data parallel for CPU backend (#23903)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-08-29 02:19:58 -07:00 |
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Li, Jiang
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67cee40da0
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[CI/Build][Bugfix] Fix Qwen VL tests on CPU (#23818)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-08-28 11:57:05 +00:00 |
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Li, Jiang
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9b0187003e
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[Bugfix] Fix cuda event usage with CPU model runner (#23643)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-08-26 17:10:42 +00:00 |
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Li, Jiang
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88016c372a
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[Bugfix] Fix pooling models on CPU backend (#23392)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-08-22 09:47:17 +00:00 |
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Li, Jiang
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7be5d113d8
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[CPU] Refactor CPU W8A8 scaled_mm (#23071)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-08-21 09:34:24 +08:00 |
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Li, Jiang
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b5dfb94fa0
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[CI/Build][Bugfix] Fix Qwen2.5 tests in CPU CI via fallback silu_and_mul to torch native implementation (#22145)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-08-03 05:34:04 -07:00 |
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Li, Jiang
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65e8466c37
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[Bugfix] Fix environment variable setting in CPU Dockerfile (#21730)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-07-28 11:02:39 +00:00 |
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Li, Jiang
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42343f1f89
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[CI] Update CODEOWNERS for CPU and Intel GPU (#21582)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-07-24 21:58:03 -07:00 |
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Li, Jiang
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5e70dcd6e6
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[Doc] Fix CPU doc format (#21316)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-07-21 21:47:49 -07:00 |
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Li, Jiang
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a15a50fc17
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[CPU] Enable shared-memory based pipeline parallel for CPU backend (#21289)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-07-21 09:07:08 -07:00 |
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Li, Jiang
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e3a0e43d7f
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[bugfix] Fix auto thread-binding when world_size > 1 in CPU backend and refactor code (#21032)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-07-19 05:13:55 -07:00 |
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Li, Jiang
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b1235c3e10
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[Bugfix] Lazy import fused_experts in BitsAndBytesMoEMethod to avoid break not-cuda-alike devices (#20822)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-07-11 20:52:05 -07:00 |
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Li, Jiang
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66177189c5
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[Bugfix] Add missing field to TritonLanguagePlaceholder (#20812)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-07-11 05:25:11 -07:00 |
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Li, Jiang
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e59ba9e142
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[CI/Build] Enlarge tolerance for a CPU multi-modal test (#20684)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-07-09 17:48:52 +00:00 |
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