 Canlin Guoandyewentao256
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a02984ed47
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[Perf][Qwen] Replace MOE all-reduce with reduce-scatter (#47006)
Signed-off-by: gcanlin <canlinguosdu@gmail.com>
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: yewentao256 <zhyanwentao@126.com>
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2026-07-12 06:14:49 +00:00 |
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19069bcbd5
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FP32 router GEMV optimization (#48335)
Signed-off-by: peiyuanz <peiyuanz@inferact.ai>
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
Co-authored-by: peiyuanz <peiyuanz@inferact.ai>
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: zhouzhou <zhouzhou@zhouzhoudeMacBook-Pro.local>
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2026-07-11 13:07:48 +00:00 |
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Qiming ZhangandKunshang Ji
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0b6636cbcb
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[XPU]remove is_xxx from moe class and bump up kernels (#48079)
Signed-off-by: mayuyuace <qiming1.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-07-11 09:27:13 +00:00 |
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Jimmy Lee
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092387963c
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[BugFix] weights processing peak memory reduction for nvfp4 MoE layers (#46276)
Signed-off-by: Jimmy Lee <hirejimmylee@gmail.com>
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2026-07-11 02:05:35 +00:00 |
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Joe Rowellandmgoin
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1bf3997eae
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[Quantization] Bound peak memory when repacking FP4 MoE weights for Marlin (#47851)
Signed-off-by: Joe Rowell <joerowell4@gmail.com>
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: mgoin <mgoin64@gmail.com>
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2026-07-10 19:46:13 -06:00 |
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Jiangyun Zhu
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300e33797f
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[Perf] fuse more rmsnorm and all-reduce in qwen3.5 (#46998)
Signed-off-by: zjy0516 <riverclouds.zhu@qq.com>
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2026-07-10 15:37:51 +08:00 |
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Yan XuandJingyi Yang
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95ed0feaa5
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DCP supports hybrid attention (#40996)
Signed-off-by: YanXu <yancey.yx@alibaba-inc.com>
Signed-off-by: Jingyi Yang <girasoleyang@gmail.com>
Co-authored-by: Jingyi Yang <girasoleyang@gmail.com>
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2026-07-09 21:34:45 -07:00 |
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gnovack
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f1a5adddb8
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update marlin M size for EP (#48144)
Signed-off-by: gnovack <novackgm@gmail.com>
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2026-07-09 23:52:52 +00:00 |
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bc44f9feb7
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[ROCm][CI][MoE] Fix double-transpose of fused w3 expert weights (#47874)
Signed-off-by: stefankoncarevic <stefan.koncarevic@amd.com>
Signed-off-by: Andreas Karatzas <akaratza@amd.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-07-08 16:59:28 -07:00 |
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Martin HickeyandHarry Mellor
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6cf7b26bd4
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[docs] Fix the docs build (#48008)
Signed-off-by: Martin Hickey <martin.hickey@ie.ibm.com>
Co-authored-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2026-07-08 15:47:22 -07:00 |
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Thien Tran
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0d2f4e7c9c
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Allow FlashInfer A2A backends for TRTLLM FP8 MoE Modular (#46661)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
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2026-07-08 14:58:39 -07:00 |
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Kaihang Jiang
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089e412878
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[Perf] Integrate TRTLLM BF16 MoE Modular Kernel (#45182)
Signed-off-by: Kaihang Jiang <kaihangj@login-lyris02.lyris.clusters.nvidia.com>
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2026-07-09 01:36:14 +04:00 |
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Martin VitandMatthew Bonanni
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c2ecd0f888
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Fix FlashAttention MLA prefill V unpadding (#42642)
Signed-off-by: Martin Vit <martin@voipmonitor.org>
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
Co-authored-by: Matthew Bonanni <mbonanni@redhat.com>
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2026-07-08 15:22:20 +00:00 |
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572b25b03e
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[Bug] Fix Batched DeepGEMM (#47884)
Signed-off-by: Robert Shaw <robertgshaw2-redhat@dgx-b200-02.mgmt.accl-001.lab.rdu2.dc.redhat.com>
Co-authored-by: Robert Shaw <robertgshaw2-redhat@dgx-b200-02.mgmt.accl-001.lab.rdu2.dc.redhat.com>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-07-08 09:05:03 -04:00 |
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rasmith
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934eeaecfb
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[CI/Build][BugFix][The Rock] Fix get_ssm_device_name to return sanitized, usable filename (#47781)
Signed-off-by: Randall Smith <Randall.Smith@amd.com>
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2026-07-08 12:12:54 +00:00 |
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vanshbhatia-amdandvanshbhatia-amd
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db39d60010
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Add tuned selective_state_update float32 config for AMD Instinct MI355 (#47943)
Signed-off-by: vanshbhatia-amd <210711135+vanshbhatia-amd@users.noreply.github.com>
Co-authored-by: vanshbhatia-amd <210711135+vanshbhatia-amd@users.noreply.github.com>
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2026-07-08 11:41:26 +00:00 |
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vanshbhatia-amdandvanshbhatia-amd
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eeaf23107f
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[ROCm] Add tuned selective_state_update float32 config for AMD Instinct MI300X (#47947)
Signed-off-by: vanshbhatia-amd <210711135+vanshbhatia-amd@users.noreply.github.com>
Co-authored-by: vanshbhatia-amd <210711135+vanshbhatia-amd@users.noreply.github.com>
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2026-07-08 11:09:02 +00:00 |
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vanshbhatia-amdandvanshbhatia-amd
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1f4ad059d1
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[ROCm] Add tuned selective_state_update float16 config for AMD Instinct MI300X (#47945)
Signed-off-by: vanshbhatia-amd <210711135+vanshbhatia-amd@users.noreply.github.com>
Co-authored-by: vanshbhatia-amd <210711135+vanshbhatia-amd@users.noreply.github.com>
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2026-07-08 11:03:58 +00:00 |
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Hongxia Yang
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2c64b4c1cc
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[ROCm] fixed aiter master flag and expert parallelism compatibility on minimax-m3-mxfp8 (#47158)
Signed-off-by: Hongxia Yang <hongxia.yang@amd.com>
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2026-07-08 15:26:17 +08:00 |
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Wei ZhaoandYongye Zhu
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2afa3f7e95
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[Perf] Minimax M3 - Support cross-layer allreduce-norm fusion (#47631)
Signed-off-by: wzhao18 <wzhao18.sz@gmail.com>
Co-authored-by: Yongye Zhu <zyy1102000@gmail.com>
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2026-07-07 21:16:32 -07:00 |
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Ethan Yangandamd-ethany
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d9e57ea82e
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[ROCm][Perf] MXFP8 dense-linear + grouped-MoE GEMM optimizations for MiniMax-M3 (#46117)
Signed-off-by: amd-ethany <amd-ethany@users.noreply.github.com>
Co-authored-by: amd-ethany <amd-ethany@users.noreply.github.com>
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2026-07-08 04:03:34 +00:00 |
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yzong-rh
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7d2ce5750e
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[Bugfix] Patch Hopper MXFP4 OOB scales reads leading to NaN (#47910)
Signed-off-by: Yifan Zong <yzong@redhat.com>
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2026-07-07 22:51:22 +00:00 |
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vanshbhatia-amdandvanshbhatia-amd
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c8c2f838e7
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Add tuned selective_state_update config for AMD Instinct MI355 (#47767)
Signed-off-by: vanshbhatia-amd <210711135+vanshbhatia-amd@users.noreply.github.com>
Co-authored-by: vanshbhatia-amd <210711135+vanshbhatia-amd@users.noreply.github.com>
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2026-07-07 22:19:08 +00:00 |
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danielafrimi
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0a2965b1b3
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[BugFix] Fix ModelOpt mixed-precision quantization for sparse quantized_layers configs. (#47318)
Signed-off-by: Daniel Afrimi <dafrimi@nvidia.com>
Signed-off-by: <dafrimi@nvidia.com>
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2026-07-07 11:45:13 +00:00 |
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Harry Mellor
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0ed05b6f82
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[CI] Fix Transformers modeling backend LoRA test (#47832)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2026-07-07 11:40:00 +00:00 |
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c85d72076a
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[HARDWARE][POWER] optimize math functions of VSX power (#47321)
Signed-off-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com>
Signed-off-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
Signed-off-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Signed-off-by: Rukhaiya <bibirukhaiya123@gmail.com>
Co-authored-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com>
Co-authored-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
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2026-07-07 09:35:47 +00:00 |
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Netanel Haberandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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066f02ae94
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[MoE] FI autotuning: max bucket = max token count [e.g. DP_size*MNBT] (#47427)
Signed-off-by: Netanel Haber <58652339+netanel-haber@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-07-07 12:08:36 +03:00 |
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Jee Jee Li
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5d23ca47ab
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[Kernel] Applies routed_scaling_factor internally (#47408)
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
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2026-07-07 02:00:54 -07:00 |
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Micah WilliamsonandAndreas Karatzas
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dd5c299fbe
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[ROCm][Bugfix] Convert ModelOpt FP8 per-channel weights to e4m3fnuz on MI300/MI325 (#47201)
Signed-off-by: Micah Williamson <micah.williamson@amd.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
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2026-07-06 23:24:58 -07:00 |
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Rahul Vishwakarma
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9dd2465896
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feat(cpu): add CPU support for Mamba ShortConv (#35059)
Signed-off-by: Rahul Vishwakarma <Rahul.Vishwakarma2@ibm.com>
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2026-07-07 10:47:08 +08:00 |
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Jinzhen Linandmgoin
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d891b9bd51
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[Quantization] add humming moe backend to all dense/moe oracles (#41652)
Signed-off-by: Jinzhen Lin <jinzhen.ljz@antgroup.com>
Co-authored-by: mgoin <mgoin64@gmail.com>
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2026-07-06 13:36:07 -07:00 |
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Andrii SkliarandAndrii Skliar
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b1384f5ec6
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Enable B12x backend for non-gated MoEs (like Nemotron) (#43328)
Signed-off-by: Andrii Skliar <askliar@nvidia.com>
Co-authored-by: Andrii Skliar <askliar@nvidia.com>
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2026-07-06 12:40:07 -07:00 |
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Wentao Ye
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b1c6dba558
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[Refactor] Remove multiple dead code (#47329)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
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2026-07-06 07:54:08 -07:00 |
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Kunshang JiandHarry Mellor
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07f9baf756
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Revert "[Platform] Replace torch.cuda.Event with torch.Event (#47140)" (#47668)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
Co-authored-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2026-07-06 14:18:33 +01:00 |
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Zhenzhong Xuandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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d9c1767cd4
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[INC][ARK] Direct Register Custom Op for ARK (#46361)
Signed-off-by: Zhenzhong1 <zhenzhong.xu@intel.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-07-06 13:45:50 +08:00 |
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Fadi Arafeh
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f1073c050c
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[CPU][BugFix] Multiple fixes to w4a8_int8 CPU MoE path (#46739)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
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2026-07-06 05:39:20 +00:00 |
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alex101-opsandzc02384840
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f2aaf59151
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[Feature] Support MTP speculative decoding for Bailing hybrid models (#44880)
Signed-off-by: zc02384840 <zc02384840@antgroup.com>
Co-authored-by: zc02384840 <zc02384840@antgroup.com>
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2026-07-06 10:38:50 +08:00 |
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Cheng Jiangandchengvjiang
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95a248faed
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[Attention Backend] HPC_ATTN backend support mtp and dynamic scheduled attention (#47433)
Signed-off-by: chengvjiang <chengvjiang@tencent.com>
Co-authored-by: chengvjiang <chengvjiang@tencent.com>
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2026-07-05 18:18:25 -07:00 |
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Wentao YeandCanlin Guo
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b6cc46ec3b
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[Feature] Support sequence parallel without the need for DP, 1.9%~5.0% E2E Throughput Improvement (#47070)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Signed-off-by: gcanlin <canlinguosdu@gmail.com>
Co-authored-by: Canlin Guo <canlinguosdu@gmail.com>
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2026-07-05 05:41:30 -07:00 |
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Chaojun ZhangandCopilot
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1a308c449c
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[XPU] Add W8A8 FP8 linear kernel with multi-granularity quant support (#43645)
Signed-off-by: Chaojun,Zhang <chaojun.zhang@intel.com>
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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2026-07-04 18:10:01 +08:00 |
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sychen52andmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
67ff0ae30f
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Support nvfp4 kv with kv-cache-dtype-skip-layers sliding_window (#42890)
Signed-off-by: Shiyang Chen <shiychen@nvidia.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-07-04 02:29:13 +00:00 |
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576bf75d0e
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[AMD][EPLB] Enable EPLB for Quark OCP MXFP4 MoE (#47220)
Signed-off-by: okorzh-amd <okorzh-amd@users.noreply.github.com>
Co-authored-by: okorzh-amd <okorzh-amd@users.noreply.github.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
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2026-07-03 14:41:52 -05:00 |
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Andreas Karatzas
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3775d5fcab
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[ROCm][CI] Adding test groups for parity with upstream (#47479)
Signed-off-by: Andreas Karatzas <akaratza@amd.com>
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2026-07-03 19:15:01 +04:00 |
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Luciano MartinsandLuciano Martins
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979f5511d7
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[Bugfix][Gemma4] Keep image bidirectional attention within the sliding window (#47217)
Signed-off-by: Luciano Martins <lucianommartins@users.noreply.github.com>
Co-authored-by: Luciano Martins <lucianommartins@users.noreply.github.com>
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2026-07-02 19:57:41 -07:00 |
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Yuxuan Zhang
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178fd56094
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support GLM-5.2 gate use FP32 (#47410)
Signed-off-by: zRzRzRzRzRzRzR <Yuxuan.Zhang2@liverpool.ac.uk>
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2026-07-02 22:45:39 +08:00 |
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Hiki
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2665ed704b
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[Bugfix][Kernel] Correct FlashInfer CUTLASS MoE tuning token bound (#46838)
Signed-off-by: Haobin Guo <haobing@nvidia.com>
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2026-07-02 05:11:00 +00:00 |
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Yongye ZhuandClaude Opus 4.8
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fa248139a0
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[MoE] Plumb gemm1_alpha/beta/clamp_limit into TRT-LLM FP8 MoE (#45723)
Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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2026-07-01 14:34:05 -07:00 |
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Yongye Zhu
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d3229431f9
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[DSV4] Better MXFP8 quantization kernel (#47229)
Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
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2026-07-01 14:33:51 -07:00 |
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Harry Mellor
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e7d0fcbc09
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[CI] Fix various failures on main (#47197)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2026-07-01 10:35:34 +01:00 |
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ed41aa270a
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[ROCm][DSV4] Use aiter mHC pre/post as the default ROCm path (#43950)
Signed-off-by: Fangzhou Ai <fangzhou.ai@amd.com>
Signed-off-by: Fangzhou-Ai <fangzhouai@gmail.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-07-01 16:27:42 +08:00 |
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