iHore/vLLM
8
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity
22,991 Commits 3 Branches 0 Tags
c19c263ac8ea3fd6e1d2d689f0e4e725855d89cf
Commit Graph
79 Commits
Author SHA1 Message Date
Harry MellorandClaude Opus 5.5 21d9758459 Remove Python 3.10 support now that it is EOL (#60402) 
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
 2026-10-08 02:30:52 -07:00
Chinmay-Kulkarni-AMDandCursor Agent 533d81b4b0 [ZenCPU][Test] Add zentorch/torch version pin consistency test (#52888) 
Signed-off-by: Chinmay Kulkarni <Chinmay.Kulkarni@amd.com>
Co-authored-by: Cursor Agent <cursoragent@cursor.com>
 2026-10-06 13:12:19 +08:00
Nils MattesonSimon Momergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
 		76d3929916 [Docker] Compile Python bytecode at image build time (#55422) 
Signed-off-by: Nils Matteson <nilsmatteson@icloud.com>
Co-authored-by: Simon Mo <simon.mo@hey.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
 2026-10-01 02:20:17 +00:00
Louie Tsai ccfd1cea75 [CPU] Include vLLM Recipes tooling in release image to deploy models using vLLM Recipes (#58796) 
Signed-off-by: louie-tsai <louie.tsai@intel.com>
 2026-09-28 16:46:53 +08:00
Turner JabbourandClaude Sonnet 5 2407f405b5 [CI] Allowlist-shrink batch 1: wire 17 root-level tests + drop 5 stale watermarking entries into misc.yaml (#58055) 
Signed-off-by: Turner Jabbour <doubleujabbour@gmail.com>
Co-authored-by: Claude Sonnet 5 <noreply@anthropic.com>
 2026-09-27 22:23:46 -07:00
zhao, zhenhuiandjiang1.li 5eaa50f151 [CPU] Build CPU wheels on Ubuntu 22.04 with AMX-FP8 support (#58515) 
Signed-off-by: zhejiangxiaomai <zhenhui.zhao@intel.com>
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Co-authored-by: jiang1.li <jiang1.li@intel.com>
 2026-09-28 11:46:02 +08:00
Misha Goin 58aa2f1ef1 [Refactor] Move auxiliary files out of the repository root (#58572) 
Signed-off-by: mgoin <mgoin64@gmail.com>
 2026-09-24 12:38:56 -07:00
Li, Jiang b44895cf93 [CPU] Use pre-built triton (#58140) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
 2026-09-24 16:12:34 +08:00
Turner JabbourClaude Sonnet 5Kevin H. LuuNick Hill
 		e9f169d16b [CI] Add pre-commit check that new tests are tethered to Buildkite jobs (#54867) 
Signed-off-by: Turner Jabbour <doubleujabbour@gmail.com>
Signed-off-by: Turner <doubleujabbour@gmail.com>
Co-authored-by: Claude Sonnet 5 <noreply@anthropic.com>
Co-authored-by: Kevin H. Luu <khluu000@gmail.com>
Co-authored-by: Nick Hill <nickhill123@gmail.com>
 2026-09-21 18:36:45 -07:00
vllm-agentandkimi-no-na-wa 8644d2af2f [CI][Build] Harden triton-cpu sleef submodule fetch in CPU image build (#57871) 
Signed-off-by: kimi-no-na-wa <kimi-no-na-wa@users.noreply.github.com>
Co-authored-by: kimi-no-na-wa <kimi-no-na-wa@users.noreply.github.com>
 2026-09-21 15:30:14 -07:00
Li, Jiang 46bae7e98c [CI/Build][CPU] Fix flaky rust downloads, broken prune flag, and triton-cpu cache coupling (#56247) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
 2026-09-10 22:27:26 +08:00
Kevin H. Luu 05e52f6336 [CI] Fix ARM64 test dependency builds with GCC 15 (#55877) 
Signed-off-by: khluu <khluu000@gmail.com>
 2026-09-08 14:27:13 -07:00
zhao, zhenhui 1c344ed41e [CPU] [Feat] Add native AMX-FP8 attention impl for Diamond Rapids (#49410) 
Signed-off-by: zhejiangxiaomai <zhenhui.zhao@intel.com>
 2026-09-06 11:06:56 +08:00
Li, Jiang 8340fe1bb9 [CI/Build] Fix flaky failures in CPU CI image building (#55317) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
 2026-09-04 20:27:02 +08:00
Andy LinfootChinmay KulkarniCursorClaude Opus 4.6
 		6fdee17f84 [CI] Zen5 image build (#50314) 
Signed-off-by: Chinmay Kulkarni <Chinmay.Kulkarni@amd.com>
Signed-off-by: andy-neuma <alinfoot@redhat.com>
Co-authored-by: Chinmay Kulkarni <Chinmay.Kulkarni@amd.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com>
 2026-09-03 17:34:35 -04:00
Andrey TalmanAndrey TalmanClaudeKevin H. Luu
 		8600db5dff [CI] Build CPU image against torch nightly for TORCH_NIGHTLY runs (#48750) 
Signed-off-by: Andrey Talman <atalman@users.noreply.github.com>
Signed-off-by: Andrey Talman <atalman@fb.com>
Co-authored-by: Andrey Talman <atalman@users.noreply.github.com>
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: Kevin H. Luu <khluu000@gmail.com>
 2026-08-31 17:25:57 -07:00
Misha GoinandOpenAI Codex c9331d8064 [CI] Preserve Rust Docker cache across commits (#53290) 
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: OpenAI Codex <codex@openai.com>
 2026-08-25 11:13:36 -07:00
Bugen ZhaoOpenAI CodexNick Hill
 		83c5d59209 [Rust Frontend] Replace external protoc with pure Rust lib protox (#52892) 
Signed-off-by: Bugen Zhao <i@bugenzhao.com>
Co-authored-by: OpenAI Codex <codex@openai.com>
Co-authored-by: Nick Hill <nickhill123@gmail.com>
 2026-08-20 18:43:51 -07:00
Bugen ZhaoNick HillAndreas Karatzas
 		c89d692cb5 [Build] Propagate vLLM version to Rust binaries (#52593) 
Signed-off-by: Bugen Zhao <i@bugenzhao.com>
Co-authored-by: Nick Hill <nickhill123@gmail.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
 2026-08-17 23:37:37 -07:00
Li, Jiang 1c3633acaf [CI/Build][CPU] Shrink triton-cpu-build layer by dropping build artifacts (#52127) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
 2026-08-13 17:17:00 +08:00
Li, Jiang 373592ef57 [CPU] Ship triton-cpu wheel and fix several hardcoded pin_memory=True (#52092) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
 2026-08-13 14:40:53 +08:00
Li, Jiang 6accb779a3 [CI] Add registry layer cache to x86 CPU image build (#51911) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
 2026-08-12 17:58:01 +08:00
Li, Jiang e9cc1fd093 [CI/Build][CPU] Remove global extra index (#47687) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
 2026-07-06 13:42:01 +08:00
AgenticSpark 978de83353 [Bugfix][CPU] Ship examples/ in the CPU release image (#47447) 
Signed-off-by: liejiang <jianglie2023@gmail.com>
 2026-07-03 11:46:24 +00:00
Li, JiangandHarry Mellor 14f8660a18 [CI/Build] Add CPU test dependency pre-commit hooks (#47032) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
Co-authored-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
 2026-06-30 07:59:13 +00:00
Harry Mellor 5316638a5e Fix transient dependency issues caused by requirements/common.txt (#47015) 
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
 2026-06-29 14:20:33 -07:00
Kevin H. Luu e3e31e54b0 [Bugfix][CPU] Don't build triton-cpu on arm64 release image (#45401) 
Signed-off-by: khluu <khluu000@gmail.com>
 2026-06-12 14:51:45 -07:00
Bugen Zhao 43914dd743 [Rust Frontend] Add Python bridge for Rust tool parsers (#44624) 
Signed-off-by: Bugen Zhao <i@bugenzhao.com>
 2026-06-11 04:51:06 +00:00
Bugen Zhao fdfb2566c0 [Rust Frontend] [CI] Unify Rust artifact builds with setuptools-rust (#44981) 
Signed-off-by: Bugen Zhao <i@bugenzhao.com>
 2026-06-10 17:48:34 +08:00
Li, Jiang 980796cd07 [CI/Build][CPU] Fix flaky CI image build failure and unexpected warnings (#44852) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
 2026-06-08 11:10:06 +00:00
Li, Jiang 3f6f508e14 [Bugfix][CPU] Remove invalid extra deps (#43977) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
 2026-05-29 22:02:09 +08:00
Li, Jiang 65b7a812a2 [CPU] Experimentally enable Triton and MRV2 (#43225) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
 2026-05-22 01:48:17 -07:00
Bugen ZhaoNick HillEric CurtinDev-X25874Will.houWill.hou
 		39910f2b25 [Rust Frontend] Move code from vllm-frontend-rs (#43283) 
Signed-off-by: Bugen Zhao <i@bugenzhao.com>
Signed-off-by: Nick Hill <nickhill123@gmail.com>
Signed-off-by: Eric Curtin <eric.curtin@docker.com>
Signed-off-by: Dev-X25874 <283057883+Dev-X25874@users.noreply.github.com>
Signed-off-by: Will.hou <1205157517@qq.com>
Signed-off-by: Will.hou <willamhou@ceresman.com>
Co-authored-by: Nick Hill <nickhill123@gmail.com>
Co-authored-by: Eric Curtin <eric.curtin@docker.com>
Co-authored-by: Dev-X25874 <283057883+Dev-X25874@users.noreply.github.com>
Co-authored-by: Will.hou <1205157517@qq.com>
Co-authored-by: Will.hou <willamhou@ceresman.com>

Please see https://github.com/Inferact/vllm-frontend-rs for full original commit history.
 2026-05-21 17:21:48 -07:00
haosdent caf69823d6 [CI] Pin protoc binary in rust-build stages (#43292) 
Signed-off-by: haosdent <haosdent@gmail.com>
 2026-05-21 03:38:07 -07:00
Nick HillandBugen Zhao f2ace1d57d [Frontend][RFC] Rust front-end integration (#40848) 
Signed-off-by: Nick Hill <nickhill123@gmail.com>
Signed-off-by: Bugen Zhao <i@bugenzhao.com>
Co-authored-by: Bugen Zhao <i@bugenzhao.com>
 2026-05-21 12:24:48 +08:00
AlecandOpenAI Codex 3f1a4bb639 build: embed image provenance metadata in vLLM containers (#40653) 
Signed-off-by: Alec Flowers <aflowers@nvidia.com>
Co-authored-by: OpenAI Codex <codex@openai.com>
 2026-04-29 03:07:41 -07:00
Li, Jiang d02421a7db [CPU] Refactor CPU affinity and memory management (#39781) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
 2026-04-17 21:01:08 +08:00
Harry MellorkhluuCyrus Leungjiang1.li
 		03f8d3a548 Update to transformers v5 (#30566) 
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
Signed-off-by: khluu <khluu000@gmail.com>
Signed-off-by: Kevin H. Luu <khluu000@gmail.com>
Signed-off-by: Cyrus Leung <cyrus.tl.leung@gmail.com>
Co-authored-by: khluu <khluu000@gmail.com>
Co-authored-by: Cyrus Leung <cyrus.tl.leung@gmail.com>
Co-authored-by: jiang1.li <jiang1.li@intel.com>
 2026-04-15 16:29:15 -07:00
Li, Jiang eb92ba740a [CI/Build] Fix sentence-transformers version in CPU test (#39557) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
 2026-04-11 07:04:25 +00:00
Harry MellorandRobert Shaw fc645f1acc Add structure to requirements/ directory (#39024) 
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
Co-authored-by: Robert Shaw <114415538+robertgshaw2-redhat@users.noreply.github.com>
 2026-04-10 13:46:41 -07:00
Andrey Talman 2111997f96 [release 2.11] Update to torch 2.11 (#34644) 2026-04-07 18:55:48 -07:00
Li, Jiang 21d7ecc5b0 [CI/Build] Add audio deps in Dockerfile.cpu (#38876) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
 2026-04-03 05:05:14 +00:00
Li, Jiang 352b90c4a4 [Bugfix] Add replacement of _compute_slot_mapping_kernel on CPU (#37987) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
 2026-03-24 07:00:20 -07:00
Lalithnarayan CChinmay-Kulkarni-AMDTyler Michael SmithTyler Michael SmithClaude Sonnet 4.6
 		7acaea634c In-Tree AMD Zen CPU Backend via zentorch [1/N] (#35970) 
Signed-off-by: Lalithnarayan C <Lalithnarayan.C@amd.com>
Signed-off-by: Tyler Michael Smith <tlrmchlsmth@gmail.com>
Co-authored-by: Chinmay-Kulkarni-AMD <Chinmay.Kulkarni@amd.com>
Co-authored-by: Tyler Michael Smith <tyler@neuralmagic.com>
Co-authored-by: Tyler Michael Smith <tlrmchlsmth@gmail.com>
Co-authored-by: Claude Sonnet 4.6 <noreply@anthropic.com>
 2026-03-15 23:35:35 +00:00
arlo 8c29042bb9 [Feature] Add InstantTensor weight loader (#36139) 2026-03-14 18:05:23 +01:00
Li, Jiangandgemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com> 092ace9e3a [UX] Improve UX of CPU backend (#36968) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Li, Jiang <bigpyj64@gmail.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
 2026-03-14 09:27:29 +08:00
Maryam TahhanandLi, Jiang <jiang1.li@intel.com> f07a128413 [CPU][ARM] Add ARM BF16 cross-compilation support and improve documen… (#33079) 
Signed-off-by: Maryam Tahhan <mtahhan@redhat.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
 2026-02-15 06:33:08 -08:00
Kunshang Ji cb9574eb85 [XPU][9/N] clean up existing ipex code/doc (#34111) 
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
 2026-02-11 00:27:15 -08:00
Xinan MiaoandSouthWest7 604e3b87e8 [Feature]: Container image WORKDIR consistency (#33159) 
Signed-off-by: SouthWest7 <am1ao@qq.com>
Co-authored-by: SouthWest7 <am1ao@qq.com>
 2026-01-28 11:06:48 +08:00
Maryam TahhanandLi, Jiang <jiang1.li@intel.com> 203d0bc0c2 [CPU] Improve CPU Docker build (#30953) 
Signed-off-by: Maryam Tahhan <mtahhan@redhat.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
 2026-01-24 17:08:24 +00:00