Harry HuangandThien Tran 494663940b [Qwen4Exp] Clean up HC and PLE implementations for Qwen3.8-Flash-Next (#61454) ...

Signed-off-by: huanghaoyan.hhy <huanghaoyan.hhy@alibaba-inc.com>
Co-authored-by: Thien Tran <gau.nernst@yahoo.com.sg>

2026-10-18 19:38:21 +08:00

..

__init__.py

[Model] Support Qwen3.8-Flash-Next (#53896)

2026-08-31 05:57:56 +00:00

test_config.py

[ROCm][Qwen4Exp] Support HC and MoE sequence parallelism on ROCm (#61471)

2026-10-15 20:11:17 -05:00

test_hc_ops.py

[Perf][Qwen4Exp] Fuse HC down projection and SiLU on NVIDIA (#58957)

2026-09-28 18:51:38 +08:00

test_ple.py

[Qwen4Exp] Clean up HC and PLE implementations for Qwen3.8-Flash-Next (#61454)

2026-10-18 19:38:21 +08:00

test_qsa_amd.py

[ROCm][Perf] Fuse main QK-norm/RoPE/gate and KV-cache write into the AMD QSA prepare launch (#59732)

2026-10-09 21:14:49 +08:00

test_qsa_prepare_amd.py

[ROCm][Perf] Fuse main QK-norm/RoPE/gate and KV-cache write into the AMD QSA prepare launch (#59732)

2026-10-09 21:14:49 +08:00

test_qsa_prepare.py

[Perf][Qwen4Exp] Merge QSA QKVG and indexer QK projections (#59533)

2026-10-05 07:03:29 +00:00

test_qsa_reference.py

[Bugfix] Keep the GLM-5.3 kpool tail and Qwen4 QSA ring out of the null block (#59528)

2026-10-08 20:44:04 +00:00

test_tpsp.py

[ROCm][Qwen4Exp] Support HC and MoE sequence parallelism on ROCm (#61471)

2026-10-15 20:11:17 -05:00