6849ca696a
Signed-off-by: Andrii Skliar <askliar@nvidia.com> Signed-off-by: Luke Alonso <lalonso@gmail.com> Co-authored-by: Andrii Skliar <askliar@nvidia.com> Co-authored-by: Luke Alonso <lalonso@gmail.com>
63 lines
2.5 KiB
Markdown
63 lines
2.5 KiB
Markdown
# b12x Linear and MoE Backends
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[b12x](https://pypi.org/project/b12x/) provides optional CUDA kernels for
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NVIDIA SM120 and SM121 GPUs. Install the dependency with:
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```bash
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uv pip install "vllm[b12x]"
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```
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b12x linear kernels participate in automatic selection after established
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optimized backends and before emulation. Select the linear and MoE backends
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explicitly with:
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```bash
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vllm serve <model> \
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--linear-backend b12x \
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--moe-backend b12x
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```
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Only pass `--moe-backend b12x` for a compatible packed-weight MoE model. The
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linear and MoE backends can be selected independently.
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b12x uses MXFP8 activations by default for MXFP4 MoE and the checkpoint's
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activation format for NVFP4 MoE. MXFP4 falls back to BF16 when its A8 path does
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not support the model configuration. Set `VLLM_B12X_MOE_FP4_FORCE_A16=1` to
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force BF16 activations for either FP4 weight format.
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## Supported Configurations
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| Backend | Supported configurations |
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| ------- | ------------------------ |
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| Linear | Per-tensor FP8, 128x128 block FP8, MXFP8, NVFP4 (including W4A16), MXFP4, IQ2_XS, IQ2_XXS, and Q8_0 |
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| MoE | Tensor-parallel MXFP4 weights with BF16 or MXFP8 activations; NVFP4 weights with BF16, NVFP4, or MXFP8 activations; IQ2_XS, IQ2_XXS, and Q8_0 weights with BF16 activations |
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| Embedding | Packed Q8_0 lookup with BF16 output |
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The b12x MoE backend does not support expert parallelism, expert maps, EXL3, or NF3.
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## ModelOpt block codecs
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ModelOpt mixed-precision checkpoints select block codecs through the
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`quantization_config.quantized_layers` entries in `config.json`. Each entry
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declares `quant_algo`, `group_size`, `block_payload_bytes`, and `packing="ggml"`:
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| `quant_algo` | `group_size` | `block_payload_bytes` |
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| --- | --- | --- |
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| `IQ2_XS` | 256 | 74 |
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| `IQ2_XXS` | 256 | 66 |
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| `Q8_0` | 32 | 34 |
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Serialized matrices have uint8 shape `[N, K/group_size, block_payload_bytes]`.
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Dense preparation rearranges the encoded blocks without expanding the matrix
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to BF16. Routed experts use bias-free SiLU or non-gated ReLU²; tensor-parallel
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shards must preserve whole blocks and satisfy the kernel's alignment constraints.
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Only Q8_0 supports packed embedding lookup.
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Quantized normalization weights and other packed vectors are not supported.
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Store normalization weights as ordinary floating-point tensors and omit their
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entries from `quantization_config.quantized_layers`.
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Dense, embedding, and expert matrices remain packed. Their execution uses BF16
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activations without activation quantization. Prepare the kernels and workspaces
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before CUDA graph capture.
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