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81e1c3f183
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[XPU][MLA] Integrate XPU MLA support into the existing FLASH_ATTN_MLA backend (#58297)
Signed-off-by: baodii <di.bao@intel.com>
Signed-off-by: Zhouxiaoya25 <xiaoya.zhou@intel.com>
Signed-off-by: ZhouXiaoya25 <xiaoya.zhou@intel.com>
Co-authored-by: baodii <di.bao@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-10-15 12:47:37 +08:00 |
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zhangchengzhucufe-devandKunshang Ji
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a33d46b471
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[Bugfix][XPU] Forward softcap and alibi_slopes in xpu_ops.flash_attn_varlen_func (#58936)
Signed-off-by: zhangchengzhucufe-dev <zhangchengzhucufe@gmail.com>
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-10-12 17:10:55 +08:00 |
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df5668e5c9
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[XPU] Dispatch nn.LayerNorm to fused SYCL kernel via CustomOp (#57172)
Signed-off-by: Michal Ganczarenko <michal.ganczarenko@intel.com>
Co-authored-by: Claude Sonnet 5 <noreply@anthropic.com>
Co-authored-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
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2026-09-30 12:19:33 +00:00 |
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Michał GanczarenkoandClaude
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73c59d365b
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[XPU] Wire up SYCL apply_rotary_emb kernel in ApplyRotaryEmb (#55721)
Signed-off-by: Michal Ganczarenko <michal.ganczarenko@intel.com>
Signed-off-by: Michał Ganczarenko <michal.ganczarenko@intel.com>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-09-22 20:43:24 -07:00 |
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Harry MellorandClaude Opus 5
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8c1557a79c
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Add pydocstyle to the ruff rules (#52136)
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
Signed-off-by: Harry Mellor <hej.mellor@gmail.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-09-16 16:44:29 +00:00 |
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zofiaandKunshang Ji
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ed29dfae6e
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[XPU] Use fused_input_norm kernel in FusedInputNorm (#52945)
Signed-off-by: Zhu, Zufang <zufang.zhu@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-09-07 13:44:31 +08:00 |
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Jee Jee Li
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199cb9b964
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[Kernel] Remove unused fake implementation (#55535)
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
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2026-09-06 17:54:32 -07:00 |
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a0d3e5c16e
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[XPU] Add fused GemmaRMSNorm path for eager execution (#53678)
Signed-off-by: Huanxing <huanxing.shen@intel.com>
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-09-03 06:11:20 +08:00 |
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HuanxingandCopilot
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aeece10c06
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[Bugfix][XPU] Run GDN attention as eager break under breakable cudagraph (#51928)
Signed-off-by: Huanxing <huanxing.shen@intel.com>
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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2026-08-12 16:23:39 +08:00 |
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Chaojun ZhangandKunshang Ji
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276f0bb5c1
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[XPU] Register fake meta kernel for fp4_gemm (#50946)
Signed-off-by: Chaojun Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-08-06 17:18:42 +08:00 |
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Avery MiaoandKunshang Ji
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c67650f04b
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[XPU][DeepSeekV4]Add DeepSeek-V4 fuse_index_q SYCL kernel path (#45991)
Signed-off-by: Avery Miao <avery.miao@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-07-21 21:22:34 +08:00 |
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823eaf667d
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[XPU] FP8 o_proj with fp8_bmm and load-time scale transpose (#48334)
Signed-off-by: Wu, Xiaochang <xiaochang.wu@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-07-20 16:32:03 +08:00 |
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liuzhenweiandKunshang Ji
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8af550b399
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[BUGFIX][XPU] Update fa interface for compatibility (#45394)
Signed-off-by: zhenwei-intel <zhenwei.liu@intel.com>
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-06-12 11:45:01 +00:00 |
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Kunshang Ji
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fe1d923afc
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[BUGFIX][XPU] fix xpu flash_attn_varlen_func interface (#45110)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-06-10 17:07:40 +08:00 |
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Marceli FylcekandKunshang Ji
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f69ede495b
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[XPU][Mamba] Triton-based selective scan forward op for XPU (#43421)
Signed-off-by: Marceli Fylcek <marceli.fylcek@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-06-02 03:50:26 -07:00 |
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Chaojun ZhangandKunshang Ji
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a3a5a5ece5
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[XPU][Bugfix] Fix per_token_group_fp8_quant missing dummy args on XPU (#43930)
Signed-off-by: Chaojun,Zhang <chaojun.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-06-02 03:09:21 +00:00 |
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Qiming ZhangandKunshang Ji
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e8b5199973
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[XPU] support MTP of gdn attention (#43565)
Signed-off-by: mayuyuace <qiming1.zhang@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-05-29 17:10:24 +08:00 |
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Xiaochang WuandKunshang Ji
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8c8b1825eb
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[XPU] Enable multiple key kernels for sparse attention (#37888)
Signed-off-by: Xiaochang Wu <xiaochang.wu@intel.com>
Signed-off-by: Wu, Xiaochang <xiaochang.wu@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-05-22 12:02:51 +08:00 |
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Yan MaandKunshang Ji
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be0dcc29dc
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[XPU] remove q/k/v force contiguous for flash_attn (#40356)
Signed-off-by: Yan Ma <yan.ma@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-05-09 01:19:05 +00:00 |
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Kunshang Ji
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2ceea42958
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[XPU] use xpu topk topp sample kernel (#39285)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-05-05 18:05:17 +08:00 |
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Yuwen ZhouandKunshang Ji
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4c34b2f6fc
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[XPU] Enable torch.compile for XPU GDN attention (#39466)
Signed-off-by: yuwenzho <yuwen.zhou@intel.com>
Signed-off-by: Yuwen Zhou <yuwen.zhou@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-04-24 16:26:16 +08:00 |
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Xinyu ChenandKunshang Ji
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55842a8d69
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[XPU]fake impl for xpu fp8_gemm (#39984)
Signed-off-by: Xinyu Chen <xinyu1.chen@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-04-18 08:53:56 +08:00 |
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zofia
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fc701c8058
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[XPU][MXFP4] add mxfp4 quant op for XPU (#39857)
Signed-off-by: Zhu, Zufang <zufang.zhu@intel.com>
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2026-04-15 12:28:19 +00:00 |
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Xinyu ChenandKunshang Ji
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639402f5a2
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Support FP8 KVCache on XPU (#37731)
Signed-off-by: Xinyu Chen <xinyu1.chen@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-04-12 03:53:32 +00:00 |
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zofiaandKunshang Ji
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ad3304425b
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[XPU] add xpu backend implementation of mxfp8 quant (#38682)
Signed-off-by: Zhu, Zufang <zufang.zhu@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-04-08 08:30:35 +08:00 |
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Kunshang Ji
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14771f7150
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[XPU] support MLA model on Intel GPU (#37143)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-03-25 17:43:42 +08:00 |
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Tianmu Li
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47b7af0d87
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[Feat] Enable CompressedTensorW4A8Int for XPU (#37207)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
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2026-03-20 02:34:28 +00:00 |
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zhao, zhenhui
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4af9ed21cb
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[Bugfix](xpu): prevent “selected index k out of range” in TP decode path (#37259)
Signed-off-by: zhenzhao <zhenzhao@habana.ai>
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2026-03-17 11:14:07 +00:00 |
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Wang, Yiting
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68e1b711f1
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[XPU] Add deepseek_scaling_rope fused kernel (#36612)
Signed-off-by: yitingw1 <yiting.wang@intel.com>
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2026-03-16 12:35:08 +08:00 |
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Wuxun Zhang
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e584dce52b
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Add XPU MLA Sparse backend for DeepSeek v3.2 (#33230)
Signed-off-by: Zhang, Wuxun <wuxun.zhang@intel.com>
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2026-03-11 19:19:15 +08:00 |
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Chendi.Xue
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d72b0be33c
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[XPU]Fix for Qwen-OMNI crash (#35249)
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
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2026-02-25 07:31:07 -08:00 |
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Kunshang Ji
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cb9574eb85
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[XPU][9/N] clean up existing ipex code/doc (#34111)
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-02-11 00:27:15 -08:00 |
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