 Qiming Zhang
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901a3b091c
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fix gpt_oss pp>1 with ep (#46441)
Signed-off-by: mayuyuace <qiming1.zhang@intel.com>
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2026-06-23 16:59:11 +08:00 |
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Woosuk Kwon
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04c2a8deac
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[DeepEP V2] Fill invalid recv_topk_idx with -1 (#46432)
Signed-off-by: Woosuk Kwon <woosuk@inferact.ai>
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2026-06-22 21:45:49 -07:00 |
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Mike G
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56e5797511
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[Quant] Enable modelopt_mixed on Turing (SM75) (#45375)
Signed-off-by: Mike G <180722391+mikekg@users.noreply.github.com>
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2026-06-22 19:30:49 -07:00 |
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Michael GoinandClaude Opus 4.8
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8207ce0850
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[Bugfix] Fix humming lm_head crash and FusedMoE weight_shape coercion (#46420)
Signed-off-by: mgoin <mgoin64@gmail.com>
Signed-off-by: Michael Goin <mgoin64@gmail.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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2026-06-22 18:19:29 -07:00 |
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e48592066e
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[DeepEP V2] Bound num_max_tokens_per_rank in do_expand=False (#46404)
Signed-off-by: Woosuk Kwon <woosuk@inferact.ai>
Co-authored-by: Roy Wang <jasonailu87@gmail.com>
Co-authored-by: gnovack <novackgm@gmail.com>
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-22 18:14:53 -07:00 |
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Bowen BaoandAndreas Karatzas
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c97e8f99d6
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[ROCm][Quantization][4/N] refactor quark_moe fp8 w/ oracle (#43721)
Signed-off-by: Bowen Bao <bowenbao@amd.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
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2026-06-22 15:58:03 -07:00 |
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ZewenShen-Cohereandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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ca5b24695b
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Fix static actorder handling for compressed-tensors WNA16 MoE (#41161)
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-22 15:46:46 -07:00 |
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c0b2d8f471
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[Bugfix] FusedMoE: coerce shape-(1,) per-tensor scales to 0-D scalar … (#43362)
Signed-off-by: Varshith <kvarshithgowda@gmail.com>
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: Michael Goin <mgoin64@gmail.com>
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2026-06-22 13:26:53 -07:00 |
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Mohammad Miadh Angkad
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d1a38c2762
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[Kernel][Performance] Add FlashInfer cutedsl NVFP4 GEMM backend (#42235)
Signed-off-by: Mohammad Miadh Angkad <176301910+mmangkad@users.noreply.github.com>
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2026-06-22 16:17:18 -04:00 |
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44d95069e9
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Enable DeepSeek V4 and GLM-5.1 on SM120 (#43477)
Signed-off-by: Zihua Wu <13583761+lucifer1004@users.noreply.github.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-authored-by: Yongye Zhu <zyy1102000@gmail.com>
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2026-06-22 11:54:14 -07:00 |
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Jinzhen Linandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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e4b3da3feb
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[Quantization][CI] add humming lm-eval test (#43752)
Signed-off-by: Jinzhen Lin <jinzhen.ljz@antgroup.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-22 11:23:55 -07:00 |
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Martin Hickey
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ccd49f6821
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[MyPy] Fix mypy for vllm/lora (#41722)
Signed-off-by: Martin Hickey <martin.hickey@ie.ibm.com>
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2026-06-22 10:57:09 -04:00 |
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Liangliang Ma
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3da4a1b124
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[XPU] add awq format for INCXPULinear (#43404)
Signed-off-by: Ma, Liangliang <liangliang.ma@intel.com>
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2026-06-22 22:29:13 +08:00 |
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Yifan Qiao
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aa4990a9a2
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[Attention] Re-enable cross-layer KV cache layout for MLA via stride-aware kernels (#45111)
Signed-off-by: Yifan Qiao <yifanqiao@inferact.ai>
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2026-06-22 06:57:02 -07:00 |
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wcyandLi, Jiang <jiang1.li@intel.com>
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d2c671c29b
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[CPU][RISC-V] Add RVV micro GEMM for WNA16 (#44324)
Signed-off-by: wcy <233313160abc@gmail.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-06-22 12:53:54 +00:00 |
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Tuukka Sarvi
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89accad2cc
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[ROCm][DSV4] Disable TileLang MHC dispatch on gfx942 (#45931)
Signed-off-by: Tuukka Sarvi <tuukka.sarvi@amd.com>
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2026-06-22 09:26:54 +00:00 |
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Athrael SojuandClaude Opus 4.8
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3c8e49596c
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[Model] ColQwen3.5: fix retrieval correctness (bias + bidirectional) (#46108)
Signed-off-by: Athrael Soju <athrael.soju@gmail.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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2026-06-22 17:25:54 +08:00 |
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d14e551a53
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[Model] Remove MiniMaxText01, MiniMaxVL01, MiniMaxForCausalLM (#45993)
Signed-off-by: Xianbao QIAN <xianbao.qian@gmail.com>
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-22 15:20:46 +08:00 |
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Ma Jian
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9037498c22
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[DSV4][XPU] Pass gemm1_clamp_limit to XpuFusedMoe (#44517)
Signed-off-by: Ma Jian <jian1.ma@intel.com>
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2026-06-22 12:57:10 +08:00 |
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fxmarty-amdandAndreas Karatzas
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485bbe1c6f
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[CI] Fix missing tp_size attribute on RoutedExperts (#46163)
Signed-off-by: Felix Marty <Felix.Marty@amd.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
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2026-06-21 18:46:49 -06:00 |
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Ting SUN
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12fe2a9aac
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[Bugfix][Qwen3-VL] Fix multi-video crash with list-valued fps/num_frames (#46305)
Signed-off-by: Ting Sun <suntcrick@gmail.com>
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2026-06-21 14:31:23 -07:00 |
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Benjamin Chislett
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89bd2c14d3
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[Spec Decode] Add Qwen3 architecture support for EAGLE3 (#43132)
Signed-off-by: Benjamin Chislett <bchislett@nvidia.com>
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2026-06-21 13:55:26 -07:00 |
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Jee Jee Li
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745bba5ea8
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[Model]Fix MiniMaxM2ForCausalLM perf regression (#45935)
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
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2026-06-22 00:28:52 +08:00 |
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Matt
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a346d589f5
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[Bugfix] Fix NVFP4/OCP MX MoE emulation (#46254)
Signed-off-by: Matthew Wong <Matthew.Wong2@amd.com>
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2026-06-20 23:13:10 -05:00 |
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Nick Hill
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7df3d7dada
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[Core] Ensure memory is pinned prior to async h2d copy (#45424)
Signed-off-by: Nick Hill <nickhill123@gmail.com>
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2026-06-20 20:02:24 -07:00 |
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Tyler Michael SmithandClaude Opus 4.6
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77148992cf
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[Bugfix] Move extract_layer_index back inside is_v32 guard (#46199)
Signed-off-by: Tyler Michael Smith <tlrmchlsmth@gmail.com>
Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com>
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2026-06-20 21:19:10 +00:00 |
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L丶andmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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d272418f45
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[Perf] Optimize Qwen3-VL multi-video prompt processing (#46026)
Signed-off-by: Sirius29 <422058530@qq.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-20 07:09:18 -07:00 |
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Jared Wen
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ab66606993
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[bugfix]Indexer init skip and MTP TopK share for iteration (#45895)
Signed-off-by: JaredforReal <w13431838023@gmail.com>
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2026-06-19 09:57:51 +08:00 |
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9ea3a4015b
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[Bugfix] Fix corrupt outputs in MoE FP8 LoRA responses and MoE base model responses when LoRAs are loaded (#42120)
Signed-off-by: Nicholas Edelman <nedelman@nvidia.com>
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
Co-authored-by: Jee Jee Li <jeejeelee@inferact.ai>
Co-authored-by: Jee Jee Li <pandaleefree@gmail.com>
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2026-06-18 18:26:09 -07:00 |
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Ting SUNandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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79ca54d221
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[Bugfix][Quantization] Don't reject fp8_e5m2 KV cache for non-fp8 quantized checkpoints (#45040)
Signed-off-by: Ting Sun <suntcrick@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-18 14:18:25 -04:00 |
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Yuwen Zhou
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058cc0a8b6
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[Bugfix] Restore is_sym guard for zp in GPTQ/CT MoE to fix symmetric quant regression (#45656)
Signed-off-by: yuwenzho <yuwen.zhou@intel.com>
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2026-06-18 16:20:29 +00:00 |
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Tiezhen WANGandClaude
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d682968aa9
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[Model] Remove BambaForCausalLM (#45990)
Signed-off-by: Xianbao QIAN <xianbao.qian@gmail.com>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-06-18 06:51:00 -07:00 |
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afdcbd5d39
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[ROCm][DSv4] Functional fixes for DeepSeek V4 on MI300X/MI325X (#45681)
Signed-off-by: ganyi <ygan@amd.com>
Signed-off-by: Markus Hartikainen <markus.hartikainen@amd.com>
Signed-off-by: Tuukka Sarvi <tuukka.sarvi@amd.com>
Co-authored-by: ganyi <ygan@amd.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Markus Hartikainen <markus.hartikainen@amd.com>
Co-authored-by: Jin Tao <jintao12@amd.com>
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2026-06-18 12:21:14 +00:00 |
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8d4f54966c
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fix(quantization): Fix AWQ dequantize on Intel XPU and refactor AutoAWQ config (#42727)
Signed-off-by: Alex <alex.tech.lab@outlook.com>
Signed-off-by: AlexHuang <jihuihuang@tencent.com>
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-18 20:12:28 +08:00 |
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Yejing LaiandKunshang Ji
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8dd8b6ed78
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[XPU] Fix FP8 block-scaled scheme selection on non-CUDA platforms (#43958)
Signed-off-by: Lai, Yejing <yejing.lai@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-06-18 10:16:20 +08:00 |
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Ting SUN
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9d4b87f4f0
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[Bugfix][Model] Validate DefaultModelLoader / LoadConfig and fail with clear errors (#45196)
Signed-off-by: Ting Sun <suntcrick@gmail.com>
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2026-06-17 21:46:33 +00:00 |
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Wentao Ye
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2659f60a1a
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[Refactor] Remove dead quantization code and tests (#45454)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
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2026-06-17 16:12:01 -04:00 |
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qli88
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d112eb1ac7
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[feature] MiniMax-M3-MXFP4 support added (#45896)
Signed-off-by: Qiang Li <qiang.li2@amd.com>
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2026-06-17 18:50:48 +00:00 |
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Wentao Ye
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9c7c74bf10
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[Log] Update deepgemm log (#45857)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
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2026-06-17 15:34:22 +00:00 |
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amirkl94
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8b2b566ea7
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Feature: Enable Flashinfer non-gated MoE bf16 (#43853)
Signed-off-by: Amir Klein <203507526+amirkl94@users.noreply.github.com>
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2026-06-17 14:32:49 +00:00 |
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xaguilar-amd
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0b131b16c9
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[ROCm][AITER][Quark] Tag per-channel FP8 weights as PER_CHANNEL so AITER pre-shuffled GEMM is selected (#44626)
Signed-off-by: Xavier Aguilar <xavier.aguilarfruto@amd.com>
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2026-06-17 14:05:34 +00:00 |
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bcb518ad7a
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[quant][autoround]Refactor INC quantization into package with INCScheme orchestrator (#40601)
Signed-off-by: yiliu30 <yi4.liu@intel.com>
Signed-off-by: Zhenzhong1 <zhenzhong.xu@intel.com>
Signed-off-by: Zhenzhong Xu <zhenzhong.xu@intel.com>
Co-authored-by: n1ck-guo <heng.guo@intel.com>
Co-authored-by: Zhenzhong1 <zhenzhong.xu@intel.com>
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2026-06-17 21:51:32 +08:00 |
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Oğuzhan KIR
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fa85ead2f3
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[MM][Perf][CG] Support ViT full CUDA graph for Kimi-VL (#41992)
Signed-off-by: oguz <oguzhankir17@gmail.com>
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2026-06-17 12:14:01 +00:00 |
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Hongxia Yangandtjtanaa
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e28e8c8782
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[ROCm][Quant] Minimax-M3: Enable fp8_per_channel for bf16 weights on mi300x (#45854)
Signed-off-by: Hongxia Yang <hongxia.yang@amd.com>
Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
Co-authored-by: tjtanaa <tunjian.tan@embeddedllm.com>
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2026-06-17 12:02:40 +00:00 |
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Joel Smith
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68ff30d40e
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[Bugfix] Fixes MiniCPM-O resampler device placement to avoid tensor device mismatch (#42332)
Signed-off-by: j9smith <j.smith9103@outlook.com>
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2026-06-17 08:35:27 +00:00 |
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arghyadeep sarkar
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93bbe94d3a
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[Kernel] Add weightless RMSNorm CUDA kernels for has_weight=False (#41430) (#44109)
Signed-off-by: hello-args <args.sarkar@gmail.com>
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2026-06-16 23:45:55 -07:00 |
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Ting SUNandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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a46abb7ae6
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[Bugfix][Quantization] Reject unsupported compressed tensors KV cache schemes (#45312)
Signed-off-by: Ting Sun <suntcrick@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-17 05:08:41 +00:00 |
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2785a5e0e6
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[Bugfix][ROCm] Fix FP8 per-tensor scale rank mismatch causing Inductor assertion failure (#44912)
Signed-off-by: nehmathe2 <nehmathe2@gmail.com>
Signed-off-by: Divakar Verma <divakar.verma@amd.com>
Signed-off-by: nehmathe <nehmathe@amd.com>
Co-authored-by: TJian <tunjian.tan@embeddedllm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Co-authored-by: Divakar Verma <divakar.verma@amd.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
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2026-06-16 20:17:42 -07:00 |
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Dakai Anandmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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71bc19dbdd
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[Bugfix] Fix MoE model load OOM in FlashInfer_TRTLLM backend with sleep mode (#45589)
Signed-off-by: Dakai An <dakaian108@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-16 19:36:51 -07:00 |
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sungsoo haandThomas Parnell
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4bf699d310
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[Kernel] Support DS Mamba tail copy for MTP align mode (#45473)
Signed-off-by: Sungsoo Ha <sungsooh@nvidia.com>
Co-authored-by: Thomas Parnell <tom.parnell@gmail.com>
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2026-06-16 22:50:30 +00:00 |
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